PEF 20550 H V2.1 Infineon Technologies, PEF 20550 H V2.1 Datasheet - Page 126

• Manufacturer Part Number: PEF 20550 H V2.1
• Description: IC INTERFACE CTRLR PCM MQFP80
• Manufacturer: Infineon Technologies
• Series: ELIC®r

Specifications of PEF 20550 H V2.1

• Function: Line Card Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-SQFP
• Includes: Change Detection, Power-Up Reset Generation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF20550HV2.1XT; PEF20550HV21XP; SP000007794; SP000007795

P1D3..0
4.3
4.3.1
Demultiplexed address mode:
Access in multiplexed P-interface mode:
Reset value: xx
P0D7..0
Note: Port 0 is only available when the multiplexed Siemens/Intel type bus mode is used
4.3.2
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: Fx
Note: In order to avoid an undefined behavior of pins P1(3:0) when reprogramming
Semiconductor Group
bit 7
bit 7
P0D7
1
(ALE is switching).
PCON1-values from input to output, it is recommended to use external pull-up/
pull-down devices at pins P1(3:0).
Parallel Ports
PORT0 Data Register (PORT0)
PORT1 Data Register (PORT1)
PORT0 data 7…0.
Data sampled on the related pin with the falling RD-edge.
PORT1 data 3…0.
Write operation:
Data is output on the related pin, assuming the pin is configured in PCON1 as
an output. The data is activated with the falling WR edge. It is stable until
another write access to PORT1 is executed or PCON1 is reprogrammed. All
outputs have push-pull characteristic.
Read operation:
Data is sampled on the related pin with the falling RD-edge, assuming the pin
is configured in PCON1 as an input.
P0D6
H
H
1
P0D5
1
P0D4
1
126
P0D3
P1D3
read
read
read/write
read/write
Detailed Register Description
P0D2
P1D2
address: 43
address: 42
address: 84
address: 86
P0D1
P1D1
PEB 20550
PEF 20550
bit 0
bit 0
H
H
H
H
P1D0
P0D0
01.96