PEF 20550 H V2.1 Infineon Technologies, PEF 20550 H V2.1 Datasheet - Page 341

• Manufacturer Part Number: PEF 20550 H V2.1
• Description: IC INTERFACE CTRLR PCM MQFP80
• Manufacturer: Infineon Technologies
• Series: ELIC®r

Specifications of PEF 20550 H V2.1

• Function: Line Card Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-SQFP
• Includes: Change Detection, Power-Up Reset Generation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF20550HV2.1XT; PEF20550HV21XP; SP000007794; SP000007795

CBSR = 0010 0000
CSCR = 0000 0000
Each SICOFI-4 device must be assigned to its individual IOM-2 channels by pin-
strapping. The SICOFI-4 coefficients (filter characteristics, gain, … ) as well as other
operation parameters, are programmed via the ELIC over the IOM-2 monitor channel.
Example
Initializing 4 consecutive CFI timeslots as an analog IOM-2 channel.
Timeslots 0, 1, 2, and 3 of CFI port 2 shall represent the IOM channel 0 of port 2.
Timeslots 4, 5, 6, and 7 of CFI port 2 shall represent the IOM channel 1 of port 2. This
requires the SICOFI-4 to be pin-strapped to that slot by connecting pin TSS0 and pin
TSS1 to 0 V.
Timeslots 4 and 5 represent the two B channels that may for example be switched to the
PCM interface. Timeslots 6 and 7 represent the monitor and signaling (SIG) channels
and must be initialized in the ELIC control memory (CM):
W: MADR = FF
W:MAAR
W: MACR = 7A
W: MADR = FF
W: MAAR = 1D
W: MACR = 7B
W: MADR = FF
W: MAAR = 9C
W: MACR = 7A
W: MADR = FF
W: MAAR = 9D
W: MACR = 7A
The above steps have to be repeated for all timeslots that shall be handled by the
monitor or signaling handler of the ELIC (i.e. TS2 and TS3, TS10 and TS11, TS14
and TS15).
CTAR
Semiconductor Group
= 0000 0010
= 1C
H
H
H
H
H
H
H
H
H
H
H
H
B
B
B
= 02
= 20
= 00
; 6 bit signaling value to be transmitted in timeslot 7
; CFI address of downstream IOM port 2, timeslot 6
; writing CM with code ‘1010’
; value don’t care, e.g. FF
; CFI address of downstream IOM port 2, timeslot 7
; writing CM with code ‘1011’
; 6 bit signaling value expected upon initialization in timeslot 7
; CFI address of upstream IOM port 2, timeslot 6
; writing CM with code ‘1010’
; 6 bit signaling value expected upon initialization in timeslot 7
; CFI address of upstream IOM port 2, timeslot 7
; writing CM with code ‘1010’
H
H
H
PFS marks downstream CFI TS0
PFS marks downstream CFI bit 7, upstream bits
not shifted
64, 32, 16 kBit/s channels located on CFI TS bits
7 … 0, 7 … 4, 7 … 6
341
Application Hints
PEB 20550
PEF 20550
01.96