PEF 20550 H V2.1 Infineon Technologies, PEF 20550 H V2.1 Datasheet - Page 270

• Manufacturer Part Number: PEF 20550 H V2.1
• Description: IC INTERFACE CTRLR PCM MQFP80
• Manufacturer: Infineon Technologies
• Series: ELIC®r

Specifications of PEF 20550 H V2.1

• Function: Line Card Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-SQFP
• Includes: Change Detection, Power-Up Reset Generation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF20550HV2.1XT; PEF20550HV21XP; SP000007794; SP000007795

PEB 20550
PEF 20550
Application Hints
5.4.3
Loops
Loops between timeslots (or even sub-timeslots) of the CFI (CFI
CFI) or the PCM
interface (PCM
PCM) can easily be programmed in the control memory. It is thus
possible to establish individual loops for individual timeslots on both interfaces without
making external connections. These loops can serve for test purposes only or for real
switching applications within the system. It should be noted that such a loop connection
is always carried out over the opposite interface i.e. looping back a CFI timeslot to
another CFI timeslot occupies a spare upstream PCM timeslot and looping back a PCM
timeslot to another PCM timeslot occupies a spare downstream and upstream CFI
timeslot. The required timeslot on the opposite interface can however be switched to
high impedance in order not to disturb the external line.
5.4.3.1 CFI - CFI Loops
For looping back a timeslot of a CFI input port to a CFI output port, two connections must
be programmed:
A first connection switches the upstream CFI timeslot to a spare PCM timeslot. This
connection is programmed like a normal CFI to PCM link, i.e the MADR contains the
encoding for the upstream PCM timeslot (U/D = 1) which is written to the upstream CM
(MAAR contains the encoding for the upstream CFI timeslot (U/D = 1)). If the data should
also be transmitted at TxD#, the tristate field of that PCM timeslot can be set to low
impedance (transparent loop). If TxD# should be disabled, the tristate field of that PCM
timeslot can be set to high impedance (non-transparent loop).
The second connection switches the “upstream” PCM timeslot (contents of the upstream
data memory) back to the downstream CFI timeslot. This connection is programmed by
using exactly the same MADR value as has been used for the first connection, i.e. the
encoding for the spare upstream PCM timeslot (with U/D = 1). This MADR value is
written to the downstream CM (MAAR contains the encoding for the downstream CFI
timeslot (U/D = 0).
The following example illustrates the necessary programming steps for establishing CFI
to CFI loops.
Semiconductor Group
270
01.96