PEF 20550 H V2.1 Infineon Technologies, PEF 20550 H V2.1 Datasheet - Page 18

• Manufacturer Part Number: PEF 20550 H V2.1
• Description: IC INTERFACE CTRLR PCM MQFP80
• Manufacturer: Infineon Technologies
• Series: ELIC®r

Specifications of PEF 20550 H V2.1

• Function: Line Card Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-SQFP
• Includes: Change Detection, Power-Up Reset Generation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF20550HV2.1XT; PEF20550HV21XP; SP000007794; SP000007795

Pin No.
70
71
61
60
59
58
63
65
67
69
62
64
66
68
27
28
Pin Definitions and Functions (cont’d)
EPIC
Semiconductor Group
®
-1 Interface
Symbol
PFS
PDC
RxD0
RxD1
RxD2
RxD3
TxD0
TxD1
TxD2
TxD3
TSC0
TSC1
TSC2
TSC3
FSC
DCL
Input (I)
Output (O)
I
I
I
I
I
I
O
O
O
O
O
O
O
O
I/O
I/O
Function
PCM-Interface Frames Synchronization
PCM-Interface Data Clock
Single or double data rate.
Receive PCM-Interface Data
Time-slot oriented data is received on this pins
and forwarded into the downstream data memory
of the EPIC-1.
Transmit PCM-Interface Data
Time-slot oriented data is shifted out of the
EPIC-1s upstream data memory on this lines. For
time-slots which are flagged in the tristate data
memory or when bit OMDR:PSB is reset the
pins are set in the state high impedance.
Tristate Control
Supplies a control signal for an external driver.
These lines are "low" when the corresponding
TxD-outputs are valid. During reset these lines are
"high".
Frame Synchronization
Input or output in IOM-configuration. Direction
indication signal in SLD-mode.
Data Clock
Input or output in IOM, slave clock in SLD
configuration. In IOM-configuration single or
double data rate, single data rate in SLD-mode.
18
PEB 20550
PEF 20550
Overview
01.96