PEF 20550 H V2.1 Infineon Technologies, PEF 20550 H V2.1 Datasheet - Page 55

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PEF 20550 H V2.1

Manufacturer Part Number
PEF 20550 H V2.1
Description
IC INTERFACE CTRLR PCM MQFP80
Manufacturer
Infineon Technologies
Series
ELIC®r
Datasheet

Specifications of PEF 20550 H V2.1

Function
Line Card Controller
Interface
ISDN, PCM
Number Of Circuits
1
Voltage - Supply
5V
Current - Supply
15mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
80-SQFP
Includes
Change Detection, Power-Up Reset Generation
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Other names
PEF20550HV2.1XT
PEF20550HV21XP
SP000007794
SP000007795
transfer ((k
CSS), if there are further bytes to transfer (figure 29). When a fast DMA-controller is
used (> 16 MHz), byte n (or bytes k
Figure 26
Timing Diagram for DMA-Transfers (fast) Transmit (n < 32, remainder of a long
message or n = k
Figure 27
Timing Diagram for DMA-Transfers (slow) Transmit (n < 32, remainder of a long
message or n = k
In receive direction the behavior of pin DRQR is implemented correspondingly. If k
bytes are transferred, pin DRQR is deactivated with the rising edge of RD of DMA-
However, if 4, 8, 16 or 32 bytes have to be transferred (only these discrete values are
possible in receive direction), DRQR is deactivated with the falling edge of RD
(figure 30).
Semiconductor Group
32)
1) and it is activated again with the next rising edge of DACK (or
32)
32)
DRQT
WR
CSS,
DACK
Cycle
DRQT
WR
CSS,
DACK
Cycle
n-2
32) will be transferred immediately (figure 28).
n-2
n-1
55
n-1
n
ITD05825
Functional Description
n
ITD05826
PEB 20550
PEF 20550
01.96
32

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