ATxmega64D3 Atmel Corporation, ATxmega64D3 Datasheet - Page 108

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ATxmega64D3

Manufacturer Part Number
ATxmega64D3
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega64D3

Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
18
Input Capture Channels
18
Pwm Channels
18
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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11.8
11.9
8210B–AVR–04/10
Port Event
Alternate Port Functions
Table 11-3.
Port pins can generate an event when there is a change on the pin. The sense configurations
decide when each pin will generate events. Event generation requires the presence of a periph-
eral clock, hence asynchronous event generation is not possible. For edge sensing, the
changed pin value must be sampled once by the peripheral clock for an event to be generated.
For low level sensing, events generation will follow the pin value.
A pin change from high to low (falling edge) will not generate an event, the pin change must be
from low to high (rising edge) for events to be generated. In order to generate events on falling
edge, the pin configuration must be set to inverted I/O. A low pin value will not generate events,
and a high pin value will continuously generate events.
Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When
an alternate function is enabled this might override the normal port pin function or pin value. This
happens when other peripherals that require pins are enabled or configured to use pins. If, and
how a peripheral will override and use pins is described in section for that peripheral.
The port override signals and related logic (grey) is shown in
signals are not accessible from software, but are internal signals between the overriding periph-
eral and the port pin.
Sense settings
Rising edge
Falling edge
Both edges
Low level
Limited asynchronous sense support
Supported
Yes
Yes
No
No
Interrupt description
-
-
Pin value must be kept unchanged.
Pin-level must be kept unchanged.
Figure 11-10 on page
XMEGA D
109. These
108

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