ATxmega64D3 Atmel Corporation, ATxmega64D3 Datasheet - Page 115
ATxmega64D3
Manufacturer Part Number
ATxmega64D3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64D3
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
18
Input Capture Channels
18
Pwm Channels
18
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Manufacturer
Quantity
Price
Part Number:
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Manufacturer:
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Company:
Part Number:
ATxmega64D3-MH
Manufacturer:
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Quantity:
515
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11.14 Register Description – Multiport Configuration
11.14.1
11.14.2
8210B–AVR–04/10
MPCMASK - Multi-pin Configuration Mask Register
VPCTRLA - Virtual Port-map Control Register A
Table 11-5.
Note:
• Bit 7:0 - MPCMASK[7:0]: Multi-pin Configuration Mask
The MPCMASK register enables several pins in a port to be configured at the same time. Writing
a one to bit n allows that pin to be part of the multi-pin configuration. When a pin configuration is
written to one of the PINnCTRL registers of the port, that value is written to all the PINnCTRL
registers of the pins matching the bit pattern in the MPCMASK register for that port. It is not nec-
essary to write to one of the registers that is set by the MPCMASK register. The MPCMASK
register is automatically cleared after any PINnCTRL registers is written.
• Bit 7:4 - VP1MAP: Virtual Port 1 Mapping
These bits decide which ports should be mapped to Virtual Port 1. The registers DIR, OUT, IN
and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing the
actual port registers. See
• Bit 3:0 - VP0MAP: Virtual Port 0 Mapping
These bits decide which ports should be mapped to Virtual Port 0. The registers DIR, OUT, IN
and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing the
actual port registers. See
Bit
+0x00
Read/Write
Initial Value
Bit
+0x02
Read/Write
Initial Value
ISC[2:0]
101
110
111
1. A low pin value will not generate events, and a high pin value will continuously generate
2. Only Port A - F supports the input buffer disable option.
events.
R/W
R/W
7
0
7
0
Input/Sense Configuration
Group Configuration
INTPUT_DISABLE
R/W
R/W
6
0
6
0
VP1MAP[3:0]
Table 11-6
Table 11-6
R/W
R/W
5
0
5
0
for configuration.
for configuration.
R/W
R/W
4
0
4
0
MPCMASK[7:0]
Reserved
Reserved
Input buffer disabled
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
0
VP0MAP[3:0]
(2)
Description
R/W
R/W
1
0
1
0
XMEGA D
R/W
R/W
0
0
0
0
MPCMASK
VPCTRLA
115
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