ATxmega64D3 Atmel Corporation, ATxmega64D3 Datasheet - Page 196

• Manufacturer Part Number: ATxmega64D3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64D3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 200
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 18
• Input Capture Channels: 18
• Pwm Channels: 18
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

17.6
17.6.1
8210B–AVR–04/10
Register Description
CTRL - SPI Control Register
• Bit 7 - CLK2X: SPI Clock Double
When this bit is set the SPI speed (SCK Frequency) will be doubled in Master mode (see
17-4 on page
• Bit 6 - ENABLE: SPI Enable
Setting this bit enables the SPI modules. This bit must be set to enable any SPI operations.
• Bit 5 - DORD: Data Order
DORD decide the data order when a byte is shifted out from the Data register. When DORD is
written to one, the LSB of the data byte is transmitted first, and when DORD is written to zero,
the MSB of the data byte is transmitted first.
• Bit 4 - MASTER: Master/Slave Select
This bit selects Master mode when written to one, and Slave mode when written to zero. If SS is
configured as an input and is driven low while MASTER is set, MASTER will be cleared.
• Bit 3:2 - MODE[1:0]: SPI Mode
These bits select the transfer mode. The four combinations of SCK phase and polarity with
respect to serial data is shown in
a clock cycles (leading edge) is rising or falling, and if data setup and sample is on lading or trail-
ing edge.
When the leading edge is rising the bit SCK is low when idle, and when the leading edge is fall-
ing the SCK is high when idle.
Table 17-3.
• Bits 1:0 - PRESCALER[1:0]: SPI Clock Prescaler
These two bits control the SCK rate of the device configured in a Master mode. These bits have
no effect in Slave mode.
Bit
+0x00
Read/Write
Initial Value
MODE[1:0]
00
01
10
11
CLK2X
R/W
197).
7
0
SPI transfer modes
ENABLE
Group Configuration
R/W
6
0
0
1
2
3
DORD
R/W
5
0
Figure 17-3 on page
MASTER
R/W
4
0
Rising, Sample
Leading Edge
Falling,Sample
Rising, Setup
Falling, Setup
R/W
3
0
MODE[1:0]
196. This decide whether the first edge in
R/W
2
0
R/W
PRESCALER[1:0]
1
0
Falling, Sample
Rising, Sample
Trailing Edge
Falling, Setup
Rising, Setup
XMEGA D
R/W
0
0
CTRL
Table
196