ATxmega64D3 Atmel Corporation, ATxmega64D3 Datasheet - Page 62

• Manufacturer Part Number: ATxmega64D3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64D3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 200
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 18
• Input Capture Channels: 18
• Pwm Channels: 18
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8210B–AVR–04/10
clock or oscillator is used to derive the System Clock (i.e clock reference for the PLL when this is
used as the active system clock) and an clock or oscillator fails (stops), the device will:
If the external oscillator fails when it is not used as the System Clock source, the external oscil-
lator is automatically disabled while the system clock will continue to operate normally.
If the external clock is below 32 kHz then the failure monitor mechanism should not be enabled
in order to avoid unintentional fail detection.
When the failure monitor is enabled, it cannot be disabled until next reset.
The failure monitor is automatically disabled in all sleep modes where the external clock or oscil-
lator is stopped. During wake-up from sleep it is automatically enabled again.
The External Clock Source Failure Monitor setting is protected by the Configuration Change Pro-
tection mechanism, employing a timed write procedure for changing the system clock and
prescaler settings. For details refer to
• Switch to the 2 MHz internal oscillator, independently of any clock system lock setting.
• Reset the Oscillator Control Register and System Clock Selection Register to their default
• Set the External Clock Source Failure Detection Interrupt Flag.
• Issue a non-maskable interrupt (NMI).
values.
”Configuration Change Protection” on page
XMEGA D
12.
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