ATxmega64D3 Atmel Corporation, ATxmega64D3 Datasheet - Page 244

• Manufacturer Part Number: ATxmega64D3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64D3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 200
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 18
• Input Capture Channels: 18
• Pwm Channels: 18
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.13.3
20.13.4
8210B–AVR–04/10
INTCTRL - ADC Channel Interrupt Control registers
INTFLAGS - ADC Channel Interrupt Flag registers
Table 20-11. ADC MUXNEG Configuration, INPUTMODE[1:0] = 11, Differential with gain
• Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility reasons always write these
bits to zero when this register is written.
• Bit 3:2 – INTMODE[1:]: ADC Interrupt Mode
These bits select the interrupt mode for channel n according to
Table 20-12. ADC Interrupt mode
• Bits 1:0 – INTLVL[1:0]: ADC Interrupt Priority Level and Enable
These bits enable the ADC channel interrupt and select the interrupt level as described in
rupts and Programmable Multi-level Interrupt Controller” on page
be triggered when the IF in the INTFLAGS register is set.
• Bits 7:1 – Reserved
These bits are reserved and will always read as zero. For compatibility reasons always write
these bits to zero when this register is written.
Bit
+0x03
Read/Write
Initial Value
Bit
+0x02
Read/Write
Initial Value
INTMODE[1:0]
MUXNEG[1:0]
00
01
10
11
00
01
10
11
R
R
7
–
0
7
–
0
Group Configuration
R
R
6
–
0
6
–
0
Group Configuration
COMPLETE
BELOW
ABOVE
PIN4
PIN5
PIN6
PIN7
R
R
0
5
–
0
5
–
R
R
4
–
0
4
–
0
Interrupt mode
Conversion Complete
Compare Result Below Threshold
Reserved
Compare Result Above Threshold
R/W
R
3
0
3
–
0
INTMODE[1:0]
R/W
R
2
0
2
–
0
Table 20-12
Analog input
95. The enabled interrupt will
ADC4 pin
ADC5 pin
ADC6 pin
ADC7 pin
R/W
R
1
–
0
1
0
INTLVL[1:0]
XMEGA D
R/W
R/W
IF
0
0
0
0
INTFLAGS
INTCTRL
”Inter-
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