ATxmega64D3 Atmel Corporation, ATxmega64D3 Datasheet - Page 263

• Manufacturer Part Number: ATxmega64D3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64D3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 200
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 18
• Input Capture Channels: 18
• Pwm Channels: 18
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

22.3.6
22.3.6.1
22.3.7
22.4
8210B–AVR–04/10
PDI Controller
Serial Reception
Direction Change
BREAK detector
When a start bit is detected, the receiver starts to collect the eight data bits and shift them into
the shift register. If the parity bit does not correspond to the parity of the data bits, a parity error
has occurred. If one or both of the stop bits are low, a frame error has occurred. If the parity bit is
correct, and no frame error detected, the received data bits are parallelized and made available
for the PDI controller.
When the PDI is in TX-mode, a BREAK character signalized by the programmer will not be inter-
preted as a BREAK, but cause a generic data collision. When the PDI is in RX-mode, a BREAK
character will be recognized as a BREAK. By transmitting two successive BREAK characters
(must be separated by one or more high bits), the last BREAK character will always be recog-
nized as a BREAK, regardless of whether the PDI was in TX- or RX-mode initially.
In order to ensure correct timing of the half-duplex operation, a simple Guard Time mechanism
is added to the PDI physical interface during direction change. When the PDI changes from
operating in RX-mode to operate in TX-mode, a configurable number of additional IDLE bits are
inserted before the start bit is transmitted. The minimum transition time between RX- and TX-
mode is two IDLE cycles, and these are always inserted. Writing the Guard Time bits in the PDI
Controller’s Control Register specifies the additional Guard Time. The default Guard Time value
is +128 bits.
Figure 22-9. PDI direction change by inserting IDLE bits
The programmer will loose control of the PDI_DATA line at the point where the PDI target
changes from RX- to TX-mode. The Guard Time relaxes this critical phase of the communica-
tion. When the programmer changes from RX-mode to TX-mode, minimum a single IDLE bit
should be inserted before the start bit is transmitted.
The PDI Controller includes data transmission/reception on a byte level, command decoding,
high-level direction control, control and status register access, exception handling, and clock
switching (PDI_CLK or TCK). The interaction between a programmer and the PDI Controller is
based on a scheme where the programmer transmits various types of requests to the PDI Con-
troller, which in turn responds in a way according to the specific request. A programmer request
comes in the form of an instruction, which may be followed by one or more byte operands. The
PDI Controller response may be silent (e.g. a data byte is stored to a location within the target),
or it may involve data to be returned back to the programmer (e.g. a data byte is read from a
location within the target).
St
d2W DATA Receive (RX)
1 DATA character
Emulator to d2W
Data from
interface
P
Sp1
Sp2
IDLE bits
Dir. change
Guard time
# IDLE bits
inserted
St
d2W DATA Transmit (TX)
1 DATA character
d2W interface
to Emulator
Data from
XMEGA D
V
Sp1 Sp2
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