ATxmega64D3 Atmel Corporation, ATxmega64D3 Datasheet - Page 215

• Manufacturer Part Number: ATxmega64D3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64D3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 200
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 18
• Input Capture Channels: 18
• Pwm Channels: 18
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18.14.3
18.14.4
8210B–AVR–04/10
CTRLA – USART Control Register A
CTRLB - USART Control Register B
This bit is unused in Master SPI mode of operation.
• Bit 7:6 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 5:4 - RXCINTLVL[1:0]: Receive Complete Interrupt Level
These bits enable the Receive Complete Interrupt and select the interrupt level as described in
”Interrupts and Programmable Multi-level Interrupt Controller” on page
will be triggered when the RXCIF in the STATUS register is set.
• Bit 3:2 - TXCINTLVL[1:0]: Transmit Complete Interrupt Level
These bits enable the Transmit Complete Interrupt and select the interrupt level as described in
”Interrupts and Programmable Multi-level Interrupt Controller” on page
will be triggered when the TXCIF in the STATUS register is set.
• Bit 1:0 - DREINTLVL[1:0]: USART Data Register Empty Interrupt Level
These bits enable the Data Register Empty Interrupt and select the interrupt level as described
in
rupt will be triggered when the DREIF in the STATUS register is set.
• Bit 7:5 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 4 - RXEN: Receiver Enable
Writing this bit to one enables the USART Receiver. The Receiver will override normal port oper-
ation for the RxD pin when enabled. Disabling the Receiver will flush the receive buffer
invalidating the FERR, BUFOVF, and PERR flags.
• Bit 3 - TXEN: Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port
operation for the TxD pin when enabled. Disabling the Transmitter (writing TXEN to zero) will not
Bit
+0x03
Read/Write
Initial Value
Bit
+0x04
Read/Write
Initial Value
”Interrupts and Programmable Multi-level Interrupt Controller” on page
R
R
7
–
0
7
–
0
R
R
6
–
0
6
–
0
R/W
R
5
RXCINTLVL[1:0]
0
5
–
0
RXEN
R/W
R/W
4
0
4
0
TXEN
R/W
R/W
3
TXCINTLVL[1:0]
0
3
0
CLK2X
R/W
R/W
2
0
2
0
MPCM
95. The enabled interrupt
95. The enabled interrupt
R/W
R/W
1
DREINTLVL[1:0]
0
1
0
95. The enabled inter-
XMEGA D
TXB8
R/W
R/W
0
0
0
0
CTRLA
CTRLB
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