ATxmega64D3 Atmel Corporation, ATxmega64D3 Datasheet - Page 51

no-image

ATxmega64D3

Manufacturer Part Number
ATxmega64D3
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega64D3

Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
18
Input Capture Channels
18
Pwm Channels
18
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATXMEGA64D3
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATxmega64D3-AU
Manufacturer:
JST
Quantity:
1 000
Part Number:
ATxmega64D3-AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATxmega64D3-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATxmega64D3-AUR
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATxmega64D3-MH
Manufacturer:
Atmel
Quantity:
515
5.8.2
8210B–AVR–04/10
CHnCTRL – Event Channel n Control Register
Table 5-3.
Note:
Table 5-4.
.
• Bit 7 - Reserved
This bit is reserved and will always be read as zero. For compatibility with future devices, always
write this bit to zero when this register is written.
Bit
Read/Write
Initial Value
T/C Event E
0
0
0
1
1
1
1
CHnMUX[7:4]
0111
0111
1000
1001
1010
1011
1100
1100
1101
1101
1110
1110
1111
1111
0
0
1
0
0
1
1
1. The description of how PORTS generate events are described in
0
1
X
0
1
0
1
CHnMUX[7:0] Bit Settings (Continued)
Timer/Counter Events
R
7
0
Group Configuration
TCxn_OVF
TCxn_ERR
TCxn_CCA
TCxn_CCA
TCxn_CCA
TCxn_CCA
CHnMUX[3:0]
X
X
X
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
R/W
6
0
M
QDIRM[1:0]
X
X
X
E
E
E
X
E
X
E
X
n
n
X
X
X
X
X
X
R/W
5
0
Group Configuration
PORTE_PINn
PORTF_PINn
PRESCALER_M
See
See
See
See
See
Table 5-4
Table 5-4
Table 5-4
Table 5-4
Table 5-4
Event Type
Over-/Underflow (x = C, D, E or F) (n= 0 or 1)
Error (x = C, D, E or F) (n= 0 or 1)
(Reserved)
Capture or Compare A (x = C, D, E or F) (n= 0 or 1)
Capture or Compare B (x = C, D, E or F) (n= 0 or 1)
Capture or Compare C (x = C, D, E or F) (n= 0 or 1)
Capture or Compare D (x = C, D, E or F) (n= 0 or 1)
QDIEN
R/W
4
0
(1)
(1)
QDEN
R/W
3
0
Event Source
PORTE Pin n (n= 0, 1, 2 ... or 7)
PORTF Pin n (n= 0, 1, 2 ... or 7)
Clk
(Reserved)
(Reserved)
(Reserved)
Timer/Counter C0 event type E
Timer/Counter C1 event type E
Timer/Counter D0 event type E
(Reserved)
Timer/Counter E0 event type E
(Reserved)
Timer/Counter F0 event type E
(Reserved)
R/W
2
0
PER
divide by M (M=1 to 32768)
DIGFILT[2:0]
”Port Event” on page
R/W
1
0
XMEGA D
R/W
0
0
CHnCTRL
108.
51

Related parts for ATxmega64D3