ATxmega64D3 Atmel Corporation, ATxmega64D3 Datasheet - Page 15

• Manufacturer Part Number: ATxmega64D3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64D3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 200
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 18
• Input Capture Channels: 18
• Pwm Channels: 18
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

3.14.5
3.14.6
3.14.7
8210B–AVR–04/10
RAMPZ - Extended Z-Pointer Register
EIND - Extended Indirect Register
SPL - Stack Pointer Register Low
This register is concatenated with the Z-register for indirect addressing (LD/LDD/ST/STD) of the
whole data memory space on devices with more than 64K bytes of data memory. RAMPZ is
concatenated with the Z-register when reading (ELPM) program memory locations above the
first 64K bytes, and writing (SPM) program memory locations above the first 128K bytes of the
program memory.
When accessing data addressees below 64K bytes, reading program memory locations below
64K bytes and writing program memory locations below 128K bytes, this register is not in use.
This register is not available if the data memory including external memory and program mem-
ory in the device is less than 64K bytes.
• Bit 7:0 – RAMPZ[7:0]: Extended Z-pointer Address bits
These bits holds the 8 MSB of the 24-bit address created by RAMPZ and the 16-bit Z-register.
Only the number of bits required to address the available data and program memory is imple-
mented for each device. Unused bits will always read as zero.
This register is concatenated with the Z-register for enabling extended indirect jump (EIJMP)
and call (ECALL) to the whole program memory space devices with more than 128K bytes of
program memory. For jump or call to addressees below 128K bytes, this register is not in use.
This register is not available if the program memory in the device is less than 128K bytes.
• Bit 7:0 - EIND[7:0]: Extended Indirect Address bits
These bits holds the 8 MSB of the 24-bit address created by EIND and the 16-bit Z-register.
Only the number of bits required to access the available program memory is implemented for
each device. Unused bits will always read as zero.
The SPH and SPL register pair represent the 16-bit value SP. The SP holds the Stack Pointer
that point to the top of the Stack. After reset, the Stack Pointer points to the highest internal
SRAM address. When SPL is written all interrupts are disabled for up to four instructions or until
SPH is also written. Any pending interrupts will be executed according to their priority once inter-
rupts are enabled again.
Only the number of bits required to address the available data memory including external mem-
ory, up to 64K bytes is implemented for each device. Unused bits will always read as zero.
Bit
+0x0B
Read/Write
Initial Value
Bit
+0x0C
Read/Write
Initial Value
R/W
R/W
7
0
7
0
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
R/W
R/W
4
0
4
0
RAMPZ[7:0]
EIND[7:0]
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
0
R/W
R/W
1
0
1
0
XMEGA D
R/W
R/W
0
0
0
0
RAMPZ
EIND
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