ATxmega64D3 Atmel Corporation, ATxmega64D3 Datasheet - Page 181
ATxmega64D3
Manufacturer Part Number
ATxmega64D3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64D3
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
18
Input Capture Channels
18
Pwm Channels
18
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Quantity
Price
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515
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16.8
16.8.1
16.9
16.9.1
8210B–AVR–04/10
Register Description - TWI
Register Description - TWI Master
CTRL– TWI Common Control Register
CTRLA - TWI Master Control Register A
• Bit 7:2 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1
SCL.
• Bit 0 - EDIEN: External Driver Interface Enable
Setting this bit enables the use of the external driver interface, clearing this bit enables normal
two wire mode. See
Table 16-1.
• Bit 7:6 - INTLVL[1:0]: Interrupt Level
The Interrupt Level (INTLVL) bit select the interrupt level for the TWI master interrupts.
• Bit 5 - RIEN: Read Interrupt Enable
Setting the Read Interrupt Enable (RIEN) bit enables the Read Interrupt when the Read Interrupt
Flag (RIF) in the STATUS register is set. In addition the INTLVL bits must be unequal zero for
TWI master interrupts to be generated.
Setting this bit to one enables an internal hold time on SDA with respect to the negative edge of
Bit
+0x00
Read/Write
Initial Value
Bit
+0x00
Read/Write
Initial Value
EDIEN
0
1
- SDAHOLD: SDA Hold Time Enable.
Mode
Normal TWI
External Driver
Interface
R/W
7
–
R
0
7
0
External Driver Interface Enable
INTLVL[1:0]
Table 16-1
R/W
6
–
R
0
6
0
Comment
Two pin interface,
Slew rate control and input filter.
Four pin interface,
Standard I/O, no slew-rate control, no input filter.
for details.
RIEN
R/W
R
5
–
0
5
0
WIEN
R/W
R
4
–
0
4
0
ENABLE
R/W
R
3
–
0
3
0
R
R
2
–
0
2
–
0
SDAHOLD
R/W
R
1
0
1
–
0
XMEGA D
EDIEN
R/W
R
0
0
0
–
0
CTRLA
CTRL
181
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