ATxmega64D3 Atmel Corporation, ATxmega64D3 Datasheet - Page 290

• Manufacturer Part Number: ATxmega64D3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64D3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 200
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 18
• Input Capture Channels: 18
• Pwm Channels: 18
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23.11.1
23.11.2
23.11.2.1
23.11.2.2
23.11.3
8210B–AVR–04/10
Enabling External Programming Interface
NVM Programming
NVM Commands
Addressing the NVM
NVM Busy
NVM programming from the PDI requires enabling, and this is one the following fashion.
When the NVMEN bit in the PDI STATUS register is set the NVM interface is active from the
PDI.
When the PDI NVM interface is enabled, all the memories in the device is memory-mapped in
the PDI address space. For the reminder of this section all references to reading and writing
data or program memory addresses from PDI, refer to the memory map as shown in
on page
byte addresses. When filling the Flash or EEPROM page buffers, only the least significant bits of
the address are used to determine locations within the page buffer. Still, the complete memory
mapped address for the Flash or EEPROM page is required to ensure correct address mapping.
During programming (page erase and page write) when the NVM is busy, the complete NVM is
blocked for reading.
The NVM commands that can be used for accessing the NVM memories from external program-
ming are listed in
programming.
For external programming, the Trigger for Action Triggered Commands is to set the CMDEX bit
in the NVM CTRLA register (CMDEX). The Read Triggered Commands are triggered by a direct
or indirect Load instruction (LDS or LD) from the PDI (PDI Read). The Write Triggered Com-
mands is triggered by a direct or indirect Store instruction (STS or ST) from the PDI (PDI Write).
Section 23.11.3.1 on page 292
algorithm for each NVM operation. The commands are protected by the Lock Bits, and if Read
and Write Lock is set, only the Chip Erase and Flash CRC commands are available.
1. Load the RESET register in the PDI with 0x59 - the Reset Signature.
2. Load the correct NVM key in the PDI.
3. Poll NVMEN in the PDI Status Register (PDI STATUS) until NVMEN is set.
289. The PDI is always using byte addressing, hence all memory addresses must be
Table
23-5. This is a super-set of the commands available for self-
through
Section 23.11.3.9 on page 293
explains in detail the
XMEGA D
Figure 23-4
290