ATxmega64D3 Atmel Corporation, ATxmega64D3 Datasheet - Page 26

• Manufacturer Part Number: ATxmega64D3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64D3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 200
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 18
• Input Capture Channels: 18
• Pwm Channels: 18
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

4.12.11
8210B–AVR–04/10
STATUS - Non-Volatile Memory Status Register
• Bit 3:2 - SPMLVL[1:0]: SPM Ready Interrupt Level
These bits enable the Interrupt and select the interrupt level as described in
grammable Multi-level Interrupt Controller” on page
will be triggered when the BUSY flag in the STATUS is set to logical 0. Since the interrupt is a
level interrupt note the following.
The interrupt should not be enabled before triggering a NVM command, as the BUSY flag wont
be set before the NVM command is triggered. Since the interrupt trigger is a level interrupt, the
interrupt should be disabled in the interrupt handler.
• Bit 1:0 - EELVL[1:0]: EEPROM Ready Interrupt Level
These bits enable the EEPROM Ready Interrupt and select the interrupt level as described in
”Interrupts and Programmable Multi-level Interrupt Controller” on page
level interrupt, which will be triggered when the BUSY flag in the STATUS is set to logical 0.
Since the interrupt is a level interrupt note the following.
The interrupt should not be enabled before triggering a NVM command, as the BUSY flag wont
be set before the NVM command is triggered. Since the interrupt trigger is a level interrupt, the
interrupt should be disabled in the interrupt handler.
• Bit 7 - NVMBUSY: Non-Volatile Memory Busy
The NVMBSY flag indicates whether the NVM memory (FLASH, EEPROM, Lock-bits) is busy
being programmed. Once a program operation is started, this flag will be set and it remains set
until the program operation is completed. he NVMBSY flag will automatically be cleared when
the operation is finished.
• Bit 6 - FBUSY: Flash Section Busy
The FBUSY flag indicate whether a Flash operation (Page Erase or Page Write) is initiated.
Once a operation is started the FBUSY flag is set, and the Application Section cannot be
accessed. The FBUSY bit will automatically be cleared when the operation is finished.
• Bit 5:2 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 1 - EELOAD: EEPROM Page Buffer Active Loading
The EELOAD status flag indicates that the temporary EEPROM page buffer has been loaded
with one or more data bytes. Immediately after an EEPROM load command is issued and byte is
written to NVMDR, or a memory mapped EEPROM buffer load operation is performed, the
EELOAD flag is set, and it remains set until an EEPROM page write- or a page buffer flush oper-
ation is executed.
Bit
+0x04
Read/Write
Initial Value
BUSY
R
7
0
FBUSY
R
6
0
R
5
–
0
R
4
–
0
R
3
–
0
95. The interrupt is a level interrupt, which
R
2
–
0
EELOAD
R
1
0
95. The interrupt is a
”Interrupts and Pro-
XMEGA D
FLOAD
R
0
0
STATUS
26