SAM7S16 Atmel Corporation, SAM7S16 Datasheet - Page 138

• Manufacturer Part Number: SAM7S16
• Manufacturer: Atmel Corporation

Specifications of SAM7S16

• Flash (kbytes): 16 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 21
• Ext Interrupts: 21
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

20.3.3
20.3.4
138
SAM7S Series
Read/Write Handshake
Device Operations
The read/write handshake is done by carrying out read/write operations on two registers of the
device that are accessible through the JTAG:
Access to these registers is done through the TAP 38-bit DR register comprising a 32-bit data
field, a 5-bit address field and a read/write bit. The data to be written is scanned into the 32-bit
data field with the address of the register to the 5-bit address field and 1 to the read/write bit. A
register is read by scanning its address into the address field and 0 into the read/write bit, going
through the UPDATE-DR TAP state, then scanning out the data.
Refer to the ARM7TDMI reference manuel for more information on Comm channel operations.
Figure 20-8. TAP 8-bit DR Register
A read or write takes place when the TAP controller enters UPDATE-DR state. Refer to the IEEE
1149.1 for more details on JTAG operations.
The write handshake is done by polling the Debug Comms Control Register until the R bit is
cleared. Once cleared, data can be written to the Debug Comms Data Register.
The read handshake is done by polling the Debug Comms Control Register until the W bit is set.
Once set, data can be read in the Debug Comms Data Register.
Several commands on the Flash memory are available. These commands are summarized in
Table 20-3 on page
is reading and writing the Debug Comms Registers.
TDI
• Debug Comms Control Register: DCCR
• Debug Comms Data Register: DCDR
• The address of the Debug Comms Control Register is 0x04.
• The address of the Debug Comms Data Register is 0x05.
The Debug Comms Control Register is read-only and allows synchronized handshaking
between the processor and the debugger.
– Bit 1 (W): Denotes whether the programmer can read a data through the Debug
– Bit 0 (R): Denotes whether the programmer can send data from the Debug Comms
Comms Data Register. If the device is busy W = 0, then the programmer must poll
until W = 1.
Data Register. If R = 1, data previously placed there through the scan chain has not
been collected by the device and so the programmer must wait.
r/w
4
Address
Address
Decoder
126. Commands are run by the programmer through the serial interface that
5
0
31
Debug Comms Control Register
Debug Comms Data Register
Data
32
6175L–ATARM–28-Jul-11
0
TDO