SAM7S16 Atmel Corporation, SAM7S16 Datasheet - Page 720

• Manufacturer Part Number: SAM7S16
• Manufacturer: Atmel Corporation

Specifications of SAM7S16

• Flash (kbytes): 16 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 21
• Ext Interrupts: 21
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

40.19.2
40.19.2.1
40.19.3
40.19.3.1
40.19.4
40.19.4.1
720
SAM7S Series
JTAG
Master Clock (MCK)
Non Volatile Memory Bits (NVM Bits)
JTAG: Recommendation for TDI Pin
MCK: Limited Master Clock Frequency Ranges
NVM Bits: Write/Erase Cycles Number
TDI pin shows a weakness which does not effect the operation of the device. If this pin is driven
over 2.0V or exposed to high electrostatic voltages, the pad might be partially destroyed and this
can lead to additional continuous leakage on VDDCORE between 100 and 500 µA.
However, this does not prevent JTAG operations.
The JTAG port remains operational even if the failure on TDI has happened. Therefore the users
can develop their applications in normal conditions, except the overall system power consump-
tion might be higher. It is recommended to handle the devices carefully during PCB soldering
and to correctly ground the manufacturing equipment.
To prevent any failure on the final customer's systems, it is also recommended to tie the TDI pin
at GND in the system production release and to not pull it up, as it is shown on the SAM7S-EK
Evaluation Board schematics.
If the Flash is operating without wait states, the frequency of the Master Clock MCK must be
lower than 3 MHz or higher than 19 MHz.
If the Flash is operating with one wait state, the frequency of the Master Clock MCK must be
lower than 3 MHz or higher than 19 MHz.
If the Flash is operating with two wait states, the frequency of the Master Clock MCK must be
lower than 3 MHz or higher than 25 MHz.
If the Flash is operating with three wait states, the frequency of the Master Clock MCK must be
lower than 3 MHz or higher than 38 MHz.
If these constraints are not respected, the correct operation of the system cannot be guaranteed
and either data or prefetch abort might occur.
The maximum operating frequencies (at 30 MHz @ 0 Wait States and 55 MHz @ 1 Wait State)
as stated in
Note:
The user must ensure that the device is running at the authorized frequency by programming the
PLL properly to not run within the forbidden frequency range.
The maximum number of write/erase cycles for Non Volatile Memory bits is 100. This includes
Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
This maximum number of write/erase cycles is not applicable to 32 KB Flash memory, it remains
at10K for the Flash memory.
Problem Fix/Workaround
Problem Fix/Workaround
It is not necessary to use 2 o 3 wait states because the Flash can operate at maximum frequency
with only 1 wait state.
Table 37-24, “Embedded Flash Wait States,” on page
578, are still applicable.
6175L–ATARM–28-Jul-11