SAM7S16 Atmel Corporation, SAM7S16 Datasheet - Page 702

• Manufacturer Part Number: SAM7S16
• Manufacturer: Atmel Corporation

Specifications of SAM7S16

• Flash (kbytes): 16 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 21
• Ext Interrupts: 21
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

40.16.6
40.16.6.1
40.16.6.2
40.16.6.3
40.16.6.4
40.16.6.5
40.16.6.6
702
SAM7S Series
Serial Peripheral Interface (SPI)
SPI: Software Reset Must be Written Twice
SPI: Pulse Generation on SPCK
SPI: Bad tx_ready behavior when CSAAT=1 and SCBR = 1
SPI: LASTXFER (Last Transfer) behavior
SPI: SPCK Behavior in Master Mode
SPI: Chip Select and Fixed Mode
If a software reset (SWRSTin the SPI Control Register) is performed, the SPI may not work
properly (the clock is enabled before the chip select.
The SPI Control Register field, SWRST needs to be written twice to be set correctly.
In Master Mode, there is an additional pulse generated on SPCK when the SPI is configured as
follows:
None.
If the SPI is programmed with CSAAT = 1, SCBR(baudrate) = 1 and two transfers are performed
consecutively on the same slave with an IDLE state between them, the tx_ready signal does not
rise after the second data has been transferred in the shifter. This can imply for example, that
the second data is sent twice.
Do not use the combination CSAAT=1 and SCBR =1.
In FIXED Mode, with CSAAT bit set, and in “PDC mode” the Chip Select can rise depending on
the data written in the SPI_TDR when the TX_EMPTY flag is set. If for example, the PDC writes
a “1” in the bit 24 (LASTXFER bit) of the SPI_TDR, the chip select will rise as soon as the
TXEMPTY flag is set.
Use the CS in PIO mode when PDC mode is required and CS has to be maintained between
transfers.
SPCK pin can toggle out before the first transfer in Master Mode.
In Master Mode, MSTR bit must be set (in SPI_MR register) before configuring SPI_CSRx
registers.
In fixed Mode, if a transfer is performed through a PDC on a Chip select different from the Chip
select 0, the output spi_size sampled by the PDC will depend on the field, BITS (Bits per Trans-
fer) of SPI_CSR0 register, whatever the selected Chip select is. For example, if SPI_CSR0 is
configured for a 10-bit transfer whereas SPI_CSR1 is configured for an 8-bit transfer, when a
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
– The Baudrate is odd and different from 1
– The Polarity is set to 1
– The Phase is set to 0
6175L–ATARM–28-Jul-11