ADUC832 Analog Devices, ADUC832 Datasheet
ADUC832
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ADUC832 Summary of contents
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... VREF V XTAL1 REF GENERAL DESCRIPTION The ADuC832 is a complete, smart transducer front end, integrating a high performance self-calibrating multichannel 12-bit ADC, dual 12-bit DACs, and programmable 8-bit MCU on a single chip. The device operates from a 32 kHz crystal with an on-chip PLL, generating a high frequency clock of 16.78 MHz. This clock is, in turn, routed through a programmable clock divider from which the MCU core clock operating frequency is generated ...
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... Using The Flash/EE Data Memory .............................................. 48 ECON—Flash/EE Memory Control SFR ................................ 48 Example: Programming the Flash/EE Data Memory ............ 49 Flash/EE Memory Timing ........................................................ 49 ADuC832 Configuration SFR (CFG832) ................................ 50 User Interface to Other On-Chip ADuC832 Peripherals ......... 51 DAC .............................................................................................. 51 Using the DAC ............................................................................ 52 On-Chip PLL................................................................................... 54 PLLCON (PLL Control Register) ............................................. 54 Pulse-Width Modulator (PWM) .................................................. 55 PWMCON (PWM Control SFR) ...
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... IE (Interrupt Enable Register) ................................................... 80 IP (Interrupt Priority Register ) ................................................ 80 IEIP2 (Secondary Interrupt Enable Register) ......................... 80 Interrupt Priority ........................................................................ 81 Interrupt Vectors ......................................................................... 81 ADuC832 Hardware Design Considerations .............................. 82 Clock Oscillator ........................................................................... 82 External Memory Interface........................................................ 82 Power Supplies ............................................................................. 83 Power Consumption ................................................................... 84 Power Saving Modes ................................................................... 84 ...
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... ADuC832 REVISION HISTORY 9/09—Rev Rev. A Changes to Figure 1 .......................................................................... 1 Changed 16.77 MHz to 16.78 MHz Throughout ......................... 1 Changes to Reference Input/Output, Output Voltage Parameter, Endnote 19, and Endnote 20, Table 1 ............................................ 9 Moved Timing Specifications Section ......................................... 10 Changes to Figure 3 ........................................................................ 10 Changes to Table 3 .......................................................................... 11 Changes to Table 4 .......................................................................... 12 Changes to Table 5 .......................................................................... 13 Changes to Table 11 ........................................................................ 19 Changes to Figure 15 and Table 13 ...
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... BUF REF C REF Figure 2. ADuC832 Block Diagram (Shaded Areas are Features Not Present on the ADuC812) diagram of the ADuC832 is shown in detailed block diagram shown in The part is specified for 3 V and 5 V operation over the extended industrial temperature range and is available in a 52-lead metric quad flat package (MQFP) and a 56-lead lead frame chip scale package (LFCSP) ...
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... ADuC832 SPECIFICATIONS unless otherwise noted. Table 1. 1 Parameter ADC CHANNEL SPECIFICATIONS Accuracy Resolution Integral Nonlinearity Differential Nonlinearity 4 Integral Nonlinearity Differential Nonlinearity 4 Code Distribution Calibrated Endpoint Errors Offset Error Offset Error Match Gain Error ...
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... Rev Page ADuC832 Test Conditions/Comments Guaranteed 12-bit monotonic V range REF V range REF % of full scale on DAC1 DAC V = 2.5 V REF Of V measured at the C ...
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... ADuC832 1 Parameter 4 SCLOCK and RESET ONLY (Schmitt-Triggered Inputs T− V − T− CRYSTAL OSCILLATOR Logic Inputs, XTAL1 Only V , Input Low Voltage INL V , Input High Voltage INH XTAL1 Input Capacitance XTAL2 Output Capacitance MCU CLOCK RATE DIGITAL OUTPUTS Output High Voltage (V ...
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... Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 700,000 cycles. 18 Retention lifetime equivalent at junction temperature (T derates with junction temperature as shown in Figure 48 in the ADuC832 Flash/EE Memory Reliability section. 19 Power supply current consumption is measured in normal, idle, and power-down modes under the following conditions: Normal mode: RESET = 0 ...
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... LOAD 4 The ADuC832 internal PLL locks onto a multiple (512 times) the external crystal frequency of 32.768 kHz to provide a stable 16.78 MHz internal clock for the system. The core can operate at this frequency binary submultiple called Core_CLK, selected via the PLLCON SFR. 5 This number is measured at the default Core_CLK operating frequency of 2 ...
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... LHLL AVLL LLPL PLPH t LLIV t PLIV t PLAZ t LLAX INSTRUCTION PCL (OUT) t AVIV PCH Figure 5. External Program Memory Read Cycle Rev Page ADuC832 Variable Clock Min Max 2t − − − − 100 CK t − − − ...
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... ADuC832 Table 4. External Data Memory Read Cycle Parameter 1 Description t RD pulse width RLRH t Address valid before ALE low AVLL t Address hold after ALE low LLAX t RD low to valid data in RLDV t Data and address hold after RD RHDX t Data float after RD RHDZ t ALE low to valid data in ...
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... LLWL WLWH t AVWL t QVWX t LLAX t QVWH DATA A16 TO A23 A8 TO A15 Figure 7. External Data Memory Write Cycle Rev Page ADuC832 Variable Clock Min Max Unit 6t − 100 − − − +50 ...
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... ADuC832 Table 6. UART Timing (Shift Register Mode) Parameter 1 Description t Serial port clock cycle time XLXL t Output data setup to clock QVXH t Input data setup to clock DVXH t Input data hold after clock XHDX t Output data hold after clock XHQX 1 See Figure 8. ALE (O) TxD ...
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... SUP Figure Compatible Interface Timing Rev Page Min 4.7 4.0 0.6 100 0.6 0.6 1 ACK MSB t t DSU F t DHD t RSU REPEATED START ADuC832 Max Unit μs μs μs μs 0.9 μs μs μs μs 300 ns 300 ...
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... ADuC832 Table 8. SPI Master Mode Timing (CPHA = 1) 1 Parameter Description t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t Data input setup time before SCLOCK edge DSU t Data input hold time after SCLOCK edge ...
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... MOSI (I) t DSU DAV MSB BIT MSB IN BIT DHD Figure 11. SPI Master Mode Timing (CPHA = 0) Rev Page ADuC832 Min Typ Max 476 476 50 150 100 100 LSB ...
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... ADuC832 Table 10. SPI Slave Mode Timing (CPHA = 1) 1 Parameter Description SCLOCK edge SS t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t Data input setup time before SCLOCK edge DSU t Data input hold time after SCLOCK edge ...
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... MSB IN MOSI (I) t DSU DAV BIT 6 TO BIT 1 MSB BIT 6 TO BIT 1 t DHD Figure 13. SPI Slave Mode Timing (CPHA = 0) Rev Page ADuC832 Min Typ Max 0 330 330 50 100 100 SFS ...
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... ADuC832BCP Storage Temperature Range Junction Temperature θ Thermal Impedance (ADuC832BS) JA θ Thermal Impedance (ADuC832BCP) JA Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any ...
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... INDICATOR 41 P2.5/A13/A21 P2.4/A12/A20 DGND DGND AGND 6 37 ADuC832 DV AGND 7 36 TOP VIEW AGND 8 35 XTAL2 (Not to Scale XTAL1 REF P2.3/A11/A19 REF 11 32 P2.2/A10/A18 DAC0 DAC1 12 31 P2.1/A9/A17 13 30 P2.0/A8/A16 14 29 SDATA/MOSI Figure 15. 56-Lead LFCSP ADuC832 DD ...
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... This pin can also be used as a gate control input to Timer 1. I/O SPI Master Input/Slave Output Data I/O Pin for SPI Serial Interface (MISO). O PWM1 Voltage Output (PWM1). See the ADuC832 Configuration SFR (CFG832) section for further information. 22, 36, P Digital Positive Supply Voltage Nominal. ...
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... External Memory Addresses (A11/A19). Port 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the external 24-bit external data memory space Input to the Inverting Oscillator Amplifier. Rev Page ADuC832 ...
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... As inputs, Port 2 pins being pulled externally low sources current because of the internal pull-up resistors. O PWM1 Voltage Output (PWM1). See the ADuC832 Configuration SFR (CFG832) section for further information. I/O External Memory Addresses (A15/A23). Port 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the external 24-bit external data memory space ...
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... External Memory Address and Data (AD7). Port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory. In this application, it uses strong internal pull-ups when emitting 1s. Rev Page ADuC832 ...
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... ADuC832 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 511 1023 1535 2047 2559 ADC CODES Figure 16. Typical INL Error, V 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 511 1023 1535 2047 2559 ADC CODES Figure 17. Typical INL Error, V 1.2 1.0 0.8 0.6 0.4 0.2 0 WCN INL –0.2 – ...
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... THD = –88.0dB ENOB = 11 FREQUENCY (kHz) Figure 26. Dynamic Performance 149.79kHz 9.910kHz IN SNR = 71.0dB THD = –83.0dB ENOB = 11 FREQUENCY (kHz) Figure 27. Dynamic Performance ADuC832 821 / / ...
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... ADuC832 0.5 1.0 1.5 2.0 EXTERNAL REFERENCE (V) Figure 28. Typical Dynamic Performance vs 0.5 1.0 1.5 2.0 EXTERNAL REFERENCE (V) Figure 29. Typical Dynamic Performance vs. V – 152kHz S –75 SNR –80 –85 THD –90 –95 –100 2.5 5 REF DD – 152kHz S – ...
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... This is the amount of time it takes for the output to settle to a specified level for a full-scale input change. Digital-to-Analog Glitch Energy This is the amount of charge injected into the analog output when the inputs change state specified as the area of the glitch in nV sec. /2), excluding dc. S Rev Page ADuC832 ...
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... V very tight code distribution of 1 LSB with the majority of codes appearing in one output pin. Figure 26 and Figure 27 show typical FFT plots for the ADuC832. These plots were generated using an external clock input. The ADC is using its internal reference (2.5 V) sampling a full-scale, 10 kHz sine wave test tone input at a sampling rate of 149 ...
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... XRAM FLASH/EE PROGRAM MEMORY The ADuC832 provides Flash/EE program memory to run user code. The user can choose to run code from this internal memory or from an external program memory. If the user applies power or resets the device while the EA pin is pulled low, the part executes code from the external program space ...
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... The external data memory is discussed in more detail in the ADuC832 Hardware Design Considerations section. INTERNAL XRAM There are on-chip data memory on the ADuC832. This memory, although on chip, is also accessed via the MOVX instruc- tion. The internal XRAM are mapped into the bottom the external address space if CFG832[0] is set ...
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... It provides an interface between the CPU and all on-chip peripher- als. A block diagram showing the programming model of the ADuC832 via the SFR area is shown in Figure 35. All registers, except the program counter (PC) and the four general-purpose register banks, reside in the SFR area. The SFR registers include control, configuration, and data registers that provide an interface between the CPU and all on-chip peripherals ...
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... ADuC832 SPECIAL FUNCTION REGISTERS All registers except the program counter and the four general- purpose register banks reside in the special function register (SFR) area. The SFR registers include control, configuration, and data registers that provide an interface between the CPU and other on-chip peripherals. ...
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... RAM space without any interaction from the MCU core. This automatic capture facility can extend through external data memory space. The ADuC832 is shipped with factory programmed calibration coefficients that are automatically downloaded to the ADC on power-up, ensuring optimum ADC performance. The ADC core contains internal offset and gain calibration registers that can be hardware calibrated to minimize system errors ...
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... ADuC832 ADCCON1 (ADC Control SFR 1) SFR Address: EFH SFR Power-On Default Value: 00H Bit Addressable: No Table 16. ADCCON1 SFR Bit Designations Bit Name Description [7] MD1 The mode bit selects the active operating mode of the ADC. Set by the user to power up the ADC. Cleared by the user to power down the ADC ...
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... Temperature sensor (requires minimum of 1 μs to acquire) 1 DAC0 (only use with internal DAC output buffer on) 0 DAC1 (only use with internal DAC output buffer on) 1 AGND 0 V REF 1 DMA stop (place in XRAM location to finish DMA sequence, see the ADC DMA Mode section) Rev Page ADuC832 ...
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... ADuC832 ADCCON3 (ADC Control SFR 3) SFR Address: F5H SFR Power-On Default Value: 00H Bit Addressable: No Table 18. ADCCON3 SFR Bit Designations Bit Name Description [7] Busy The ADC busy status bit is a read-only status bit that is set during a valid ADC conversion or calibration cycle. Busy is automatically cleared by the core at the end of conversion or calibration ...
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... The Schottky diodes in Figure 40 may be necessary to limit the voltage applied to the analog input pin as per the absolute maximum ratings (see Table 12). They are not necessary if the op amp is powered from the same supply as the ADuC832 because in that case the op amp is unable to generate voltages above V ...
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... ADC. The ADuC832 powers up with its internal voltage reference in the on state. This is available at the V previously, there is a gain error between this and that of the ADC ...
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... ADuC832 core. This mode allows the ADuC832 to capture a contiguous sample stream at full ADC update rates (247 kSPS). A Typical DMA Mode Configuration Example To set the ADuC832 into DMA mode, a number of steps must be followed: 1. The ADC must be powered down. This is done by ensuring MD1 is set ADCCON1 ...
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... When the DMA mode logic is active, it takes the responsibility of storing the ADC results away from both the user and ADuC832 core logic writes the results of the ADC conversions to external memory, it takes over the external memory interface from the core ...
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... Select the channel connected to AGND via CS[3:0] and perform system offset calibration. Select the channel connected to V via CS[3:0] and perform system gain calibration. REF The ADC should be configured to use settings for an ADCCLK of divide-by-16 and divide-by-4 acquisition clocks. Rev Page ADuC832 ...
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... ADuC832 INITIATING CALIBRATION IN CODE When calibrating the ADC using ADCCON1, the ADC should be set up into the configuration in which it will be used. The ADCCON3 register can then be used to set up the device and calibrate the ADC offset and gain. MOV ADCCON1,#0ACH ;ADC on; ADCCLK set ...
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... Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. Again, the ADuC832 has been qualified in accordance with the formal JEDEC retention lifetime specification (A117 specific junction temperature (T = 55° ...
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... Figure 49. ULOAD mode can be used to upgrade your code in the field via any user defined download protocol. Configuring the SPI port on the ADuC832 as a slave possible to completely reprogram the 90 100 110 Flash/EE program memory in only 5 seconds (see the uC007 Technical Note, User Download (ULOAD) Mode) ...
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... These security modes can be enabled as part of serial download protocol as described in Technical Note uC004 or via parallel programming. The security modes available on the ADuC832 are described as follows. Lock Mode This mode locks the code memory, disabling parallel programming of the program memory ...
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... ADuC832 USING THE FLASH/EE DATA MEMORY The Flash/EE data memory is configured as 1024 pages, each of four bytes. As with the other ADuC832 peripherals, the interface to this memory space is via a group of registers mapped in the SFR space. A group of four data registers (EDATA1 to EDATA4) are used to hold the four bytes of data at each page ...
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... FFH nonetheless good programming practice to include an erase-all routine as part of any configuration/setup code running on the ADuC832. An erase all command consists of writing 06H to the ECON SFR, which initiates an erase of the 4 kB Flash/EE array. This command coded in 8051 assembly appears as: ...
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... When set the user, the internal XRAM is mapped into the lower the external address space. When set the user, the internal XRAM is not accessible and the external data memory is mapped into the lower external data memory. CFG832 (ADuC832 Configuration SFR) SFR Address: Power-On Default Value: Bit Addressable: Rev ...
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... A summary of the SFRs used to control and configure these peripherals is also given. DAC The ADuC832 incorporates two 12-bit voltage output DACs on chip. Each DAC has a rail-to-rail voltage output buffer capable of driving 10 kΩ/100 pF. Each has two selectable ranges (the internal band gap 2 ...
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... Figure 52. Endpoint Nonlinearities Due to Amplifier Saturation The endpoint nonlinearities conceptually illustrated in Figure 52 become worse as a function of output loading. Most of the ADuC832 specifications assume a 10 kΩ resistive load to ground at the DAC output. As the output is forced to source or sink more current, the nonlinear regions at the top or bottom (respectively) of Figure 52 become larger ...
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... This means that if a zero output is desired during power-up or power-down transient conditions, then a pull- down resistor must be added to each DAC output. Assuming this resistor is in place, the DAC outputs remain at ground potential whenever the DAC is disabled. Rev Page ADuC832 DAC0 ADuC832 DAC1 Figure 55. Buffering the DAC Outputs ...
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... ADuC832 ON-CHIP PLL The ADuC832 is intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple (512) of this to provide a stable 16.78 MHz clock for the system. The core can operate at this frequency or at binary submultiples allow power saving in cases where maximum core performance is not required ...
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... PULSE-WIDTH MODULATOR (PWM) The PWM on the ADuC832 is a highly flexible PWM offering programmable resolution and an input clock, and can be confi- gured for any one of six different modes of operation. Two of these modes allow the PWM to be configured as a Σ-Δ DAC with bits of resolution. A block diagram of the PWM is shown in Figure 56 ...
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... ADuC832 PWM MODES OF OPERATION MODE 0: PWM DISABLED The PWM is disabled, allowing P2.6 and P2 used as normal. MODE 1: SINGLE VARIABLE RESOLUTION PWM In Mode 1, both the pulse length and the cycle time (period) are programmable in user code, allowing the resolution of the PWM to be variable. ...
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... PWM0H/L = C000H 60µs 16-BIT 16-BIT 4MHz 16-BIT 0, 3/4, 1/2, 1/4, 0 16-BIT PWM1H/L = 4000H Rev Page ADuC832 PWM1L PWM COUNTERS PWM1H PWM0L PWM0H 0 P2.6 P2.7 Figure 61. PWM Mode 5 down − AV /2. For best results, this DD DD CARRY OUT AT P2 ...
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... To configure this pin as a digital input, the bit must be cleared, for example, CLR P1.5. This line is active low. Data is only received or transmitted in slave mode when the SS pin is low, allowing the ADuC832 to be used in single master, multislave SPI configurations. If CPHA = 1, then the SS input may be permanently pulled low. With CPHA ...
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... SPIDAT register. The SCLOCK bit rate is determined by SPR0 and SPR1 in SPICON. It should also be noted that the SS pin is not used in master mode. If the ADuC832 needs to assert the SS pin on an external slave device, a port digital output pin should be used. ...
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... ADuC832 2 I C-COMPATIBLE INTERFACE The ADuC832 supports a fully licensed interface is implemented as a full hardware slave and soft- ware master. SDATA is the data I/O pin and SCLOCK is the serial clock. These two pins are shared with the MOSI and SCLOCK pins of the on-chip SPI interface. Therefore, the user can only enable one interface or the other at any given time (see SPE in SPICON in Table 28) ...
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... The I C interface is enabled by clearing the SPE bit in SPICON. Slave mode is enabled by clearing the I2CM bit in I2CCON. The ADuC832 has a full hardware slave. In slave mode, the I address is stored in the I2CADD register. Data received transmitted is stored in the I2CDAT register. Once enabled in I start condition ...
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... ADuC832 DUAL DATA POINTERS The ADuC832 incorporates two data pointers. The second data pointer is a shadow data pointer and is selected via the data pointer control SFR (DPCON). DPCON also includes features such as automatic hardware postincrement and postdecrement, as well as automatic data pointer toggle. DPCON is described in Table 30 ...
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... POWER SUPPLY MONITOR As its name suggests, the power supply monitor, once enabled, monitors the DV supply on the ADuC832. It indicates when DD any of the supply pins drop below one of four user-selectable voltage trip points from 2. 4.37 V. For correct operation of the power supply monitor function greater than 2 ...
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... ADuC832 WATCHDOG TIMER The purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the ADuC832 enters an erroneous state, possibly due to a programming error or electrical noise. The watchdog function can be disabled by clearing the watchdog enable (WDE) bit in the watchdog control (WDCON) SFR ...
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... INTVAL SFR, the TII bit (TIMECON[2]) is set and generates an interrupt if enabled. If the ADuC832 is in power-down mode, again with the TIC interrupt enabled, the TII bit wakes up the device and resumes code execution by vectoring directly to the TIC interrupt service vector address at 0053H ...
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... ADuC832 INTVAL (USER TIME INTERVAL SELECT REGISTER) SFR Address: A6H Power-On Default Value: 00H Bit Addressable: No Valid Value 255 decimal User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON[2]) is set and generates an interrupt if enabled ...
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... SFR bit definitions. PARALLEL I/O The ADuC832 uses four input/output ports to exchange data with external devices. In addition to performing general-purpose I/O, some ports are capable of external memory operations whereas others are multiplexed with alternate functions for the peripheral features on the device ...
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... ADuC832 them drive a logic low output voltage (V sinking 1.6 mA. P2.6 and P2.7 can also be used as PWM outputs. If they are selected as the PWM outputs via the CFG832 SFR, the PWM outputs overwrite anything written to P2.6 or P2.7. ADDR READ CONTROL LATCH INTERNAL D Q BUS WRITE LATCH ...
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... Jump if bit = 1 and clear bit, for example, JBC P1.1, LABEL Complement bit, for example, CPL P3.0 Increment, for example, INC P2 Decrement, for example, DEC P2 Decrement and jump if not zero, for example, DJNZ P3, LABEL 1 Move carry to Bit Y of Port X 1 Clear Bit Y of Port X 1 Set Bit Y of Port X ADuC832 ...
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... ADuC832 TIMERS/COUNTERS The ADuC832 has three 16-bit timer/counters: Timer 0, Timer 1, and Timer 2. The timer/counter hardware has been included on chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in software. Each timer/counter consists of two 8-bit registers THx and TLx ( and 2). All three can be configured to operate either as timers or event counters ...
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... TH0 is the Timer 0 high byte and TL0 is the low byte. The SFR addresses for TH0 and TL0 are 8CH and 8AH, respectively. TH1 and TL1 TH1 is the Timer 1 high byte and TH0 is the low byte. The SFR addresses for TH1 and TL1 are 8DH and 8BH, respectively. Rev Page ADuC832 ...
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... ADuC832 TIMER/COUNTER 0 AND TIMER/COUNTER 1 OPERATING MODES The following sections describe the operating modes for Timer/Counter 0 and Timer/Counter 1. Unless otherwise noted, it should be assumed that these modes of operation are the same for Timer 0 as for Timer 1. MODE 0 (13-BIT TIMER/COUNTER) Mode 0 configures an 8-bit timer/counter with a divide-by-32 prescaler ...
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... SFR addresses for TH2 and TL2 are CDH and CCH, respectively. RCAP2H and RCAP2L RCAP2H is the Timer 2 capture/reload high byte and RCAP2L is the low byte. The SFR addresses for RCAP2H and RCAP2L are CBH and CAH, respectively. Rev Page ADuC832 ...
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... ADuC832 TIMER/COUNTER OPERATION MODES The following sections describe the operating modes for Timer/ Counter 2. The operating modes are selected by bits in the T2CON SFR as shown in Table 39. Table 39. T2CON Operating Modes RCLK (or) TCLK CAP2 TR2 16-Bit Autoreload Mode In autoreload mode, there are two options, which are selected by Bit EXEN2 in T2CON ...
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... Power-On Default Value: Bit Addressable: Selected Operating Mode Mode 0: shift register, fixed baud rate (Core_CLK/2) Mode 1: 8-bit UART, variable baud rate Mode 2: 9-bit UART, fixed baud rate (Core_CLK/64) or (Core_CLK/32) Mode 3: 9-bit UART, variable baud rate Rev Page ADuC832 98H 00H Yes ...
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... ADuC832 MODE 0: 8-BIT SHIFT REGISTER MODE Mode 0 is selected by clearing both the SM0 and SM1 bits in the SCON SFR. Serial data enter and exit through RxD. TxD outputs the shift clock. Eight data bits are transmitted or received. Transmission is initiated by any instruction that writes to SBUF. ...
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... Actual % Baud Error 9709 1.14 2427 1.14 1197 0.25 1213 1.14 Rev Page ADuC832 RCAP2H RCAP2L Actual % Value Value Baud Error −1 (FFH) −27 (E5H) 19418 1.14 −1 (FFH) −55 (C9H) 9532 0.7 −1 (FFH) −218 (26H) 2405 0.21 −2 (FEH) −181 (4BH) 1199 0 ...
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... The high integer dividers in a UART block mean that high speed baud rates are not always possible using some particular crystals. For example, using a 12 MHz crystal, a baud rate of 115,200 is not possible. To address this problem, the ADuC832 has a dedicated baud rate timer (Timer 3) specifically for generating highly accurate baud rates. ...
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... Rev Page ADuC832 CD DIV T3CON T3FD % Error 0 1 81H 09H 0. 82H 09H 0. 81H 09H 0. 80H 09H ...
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... ADuC832 INTERRUPT SYSTEM The ADuC832 provides a total of nine interrupt sources with two priority levels. The control and configuration of the inter- rupt system is carried out through three interrupt-related SFRs: • IE—interrupt enable register • IP—interrupt priority register • IEIP2—secondary interrupt enable register Table 45 ...
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... The interrupt vector addresses are shown in Table 49. Table 49. Interrupt Vector Addresses Source IE0 TF0 IE1 TF1 TF2 + EXF2 ADCI ISPI/I2CI PSMI TII WDS 2 C interrupt Rev Page ADuC832 Vector Address 0003H 000BH 0013H 001BH 0023H 002BH 0033H 003BH 0043H 0053H 005BH ...
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... MHz. EXTERNAL MEMORY INTERFACE In addition to its internal program and data memories, the ADuC832 can access external program memory (such as ROM and PROM) and external data memory (SRAM). To select from which code space (internal or external program memory) to begin executing instructions, tie the EA (external access) pin high or low, respectively ...
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... Connect the ground terminal of each of these capacitors directly to the underlying ground plane. Finally, it should also be noted that, at all times, , DGND the analog and digital ground pins on the ADuC832 must be referenced to the same system ground reference point. and Rev ...
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... The user must add any currents sourced by the parallel and serial I/O pins and by the DAC to determine the total current needed at the ADuC832 supply pins. Also, current drawn from the DV supply increases by approx- DD imately 10 mA during Flash/EE erase and program cycles ...
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... To connect fast logic signals (rise/fall time < 5 ns) to any of the ADuC832 digital inputs, add a series resistor to each relevant line to keep rise and fall times longer than the ADuC832 input pins. A value of 100 Ω or 200 Ω is usually sufficient to prevent high speed signals from coupling capacitively into the ADuC832 and affecting the accuracy of ADC conversions ...
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... C1– T1 OUT C2 C2– R1 OUT V– OUT OUT Figure 94. Example ADuC832 System (MQFP Package) Rev Page DOWNLOAD/DEBUG ENABLE JUMPER (NORMALLY OPEN 1kΩ 1kΩ 2-PIN HEADER FOR EMULATION ACCESS (NORMALLY OPEN ...
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... SINGLE-PIN EMULATION MODE Also built into the ADuC832 is a dedicated controller for single-pin in-circuit emulation (ICE) using standard production ADuC832 devices. In this mode, emulation access is gained by connection to a single pin, the EA pin. Normally, this pin is hardwired either high or low to select execution from internal or external program memory space ...
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... QuickStart Plus—comprehensive development system QUICKSTART DEVELOPMENT SYSTEM The QuickStart development system is an entry-level, low cost development tool suite supporting the ADuC832. The system consists of the following PC-based (Windows® compatible) hardware and software development tools. Table 51. QuickStart Components Component ...
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... Temperature Range ADuC832BCP −40°C to +85°C ADuC832BCP-REEL −40°C to +85°C 1 ADuC832BCPZ −40°C to +85°C 1 ADuC832BCPZ-REEL −40°C to +85°C 1 ADuC832BSZ −40°C to +125°C 1 ADuC832BSZ-REEL −40°C to +125°C 1 EVAL-ADuC832QSZ RoHS Compliant Part. 2.45 1.03 MAX 0.88 0. SEATING PLANE 10° ...
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... ADuC832 NOTES Rev Page ...
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... NOTES Rev Page ADuC832 ...
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... Purchase of licensed I C components of Analog Devices or one of its sublicensed associated companies conveys a license for the purchaser under the Philips I 2 Rights to use the ADuC832 system, provided that the system conforms to the I ©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...