ADUC832 Analog Devices, ADUC832 Datasheet - Page 76

• Manufacturer Part Number: ADUC832
• Description: Precision Analog Microcontroller: 1.3MIPS 8052 MCU + 62kB Flash + 8-Ch 12-Bit ADC + Dual 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC832

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 8
• Other: PWM

ADuC832
MODE 0: 8-BIT SHIFT REGISTER MODE
Mode 0 is selected by clearing both the SM0 and SM1 bits in
the SCON SFR. Serial data enter and exit through RxD. TxD
outputs the shift clock. Eight data bits are transmitted or received.
Transmission is initiated by any instruction that writes to SBUF.
The data is shifted out of the RxD line. The eight bits are transmit-
ted with the least significant bit (LSB) first, as shown in Figure 81.
Reception is initiated when the receive enable bit (REN) is 1
and the receive interrupt bit (RI) is 0. When RI is cleared, the
data is clocked into the RxD line and the clock pulses are output
from the TxD line.
MODE 1: 8-BIT UART, VARIABLE BAUD RATE
Mode 1 is selected by clearing SM0 and setting SM1. Each data
byte (LSB first) is preceded by a start bit (0), followed by a stop
bit (1). Therefore, 10 bits are transmitted on TxD or received on
RxD. The baud rate is set by the Timer 1 or Timer 2 overflow
rate, or a combination of the two (one for transmission and the
other for reception).
Transmission is initiated by writing to SBUF. The write to SBUF
signal also loads a 1 (stop bit) into the ninth bit position of the
transmit shift register. The data is output bit by bit until the stop
bit appears on TxD and the transmit interrupt flag (TI) is
automatically set, as shown in Figure 82.
(SCON[1])
Reception is initiated when a 1-to-0 transition is detected on
RxD. Assuming a valid start bit was detected, character recep-
tion continues. The start bit is skipped and the eight data bits
are clocked into the serial port shift register. When all eight bits
have been clocked in, the following events occur:
•
•
•
CLOCK)
(SHIFT
(DATA
CORE
OUT)
CLK
ALE
RxD
TxD
TxD
The eight bits in the receive shift register are latched
into SBUF.
The ninth bit (stop bit) is clocked into RB8 in SCON.
The receiver interrupt flag (RI) is set.
TI
S1
START
BIT
S2
MACHINE
DATA BIT 0
Figure 81. UART Serial Port Transmission, Mode 0
Figure 82. UART Serial Port Transmission, Mode 0
CYCLE 1
S3
D0
S4
S5
D1
S6
D2
S1
DATA BIT 1
S2
MACHINE
CYCLE 2
D3
S3
S4
D4
MACHINE
D5
CYCLE 7
THAT IS, READY FOR MORE DATA
DATA BIT 6
S4
D6
S5
S6
SET INTERRUPT
D7
S1
S2
STOP BIT
MACHINE
DATA BIT 7
CYCLE 8
S3
S4
S5
S6
Rev. A | Page 76 of 92
These events occur only if the following conditions are met at
the time the final shift pulse is generated:
•
•
If either of these conditions is not met, the received frame is
irretrievably lost, and RI is not set.
MODE 2: 9-BIT UART WITH FIXED BAUD RATE
Mode 2 is selected by setting SM0 and clearing SM1. In this
mode, the UART operates in 9-bit mode with a fixed baud rate.
The baud rate is fixed at Core_CLK/64 by default, although by
setting the SMOD bit in PCON, the frequency can be doubled
to Core_CLK/32. Eleven bits are transmitted or received, a start
bit (0), eight data bits, a programmable ninth bit, and a stop bit
(1). The ninth bit is most often used as a parity bit, although it
can be used for anything, including a ninth data bit if required.
To transmit, the eight data bits must be written into SBUF. The
ninth bit must be written to TB8 in SCON. When transmission
is initiated, the eight data bits (from SBUF) are loaded onto the
transmit shift register (LSB first). The contents of TB8 are loaded
into the ninth bit position of the transmit shift register. The
transmission starts at the next valid baud rate clock. The TI flag
is set as soon as the stop bit appears on TxD.
Reception for Mode 2 is similar to that of Mode 1. The eight
data bytes are input at RxD (LSB first) and loaded onto the
receive shift register. When all eight bits have been clocked in,
the following events occur:
•
•
•
These events occur only if the following conditions are met at
the time the final shift pulse is generated:
•
•
If either of these conditions is not met, the received frame is
irretrievably lost, and RI is not set.
MODE 3: 9-BIT UART WITH VARIABLE BAUD RATE
Mode 3 is selected by setting both SM0 and SM1. In this mode,
the 8051 UART serial port operates in 9-bit mode with a variable
baud rate determined by either Timer 1 or Timer 2. The operation
of the 9-bit UART is the same as for Mode 2 but the baud rate
can be varied as for Mode 1.
In all four modes, transmission is initiated by any instruction
that uses SBUF as a destination register. Reception is initiated in
Mode 0 by the condition RI = 0 and REN = 1. Reception is
initiated in the other modes by the incoming start bit if REN = 1.
RI = 0 and either SM2 = 0 or SM2 = 1
The received stop bit = 1
The eight bits in the receive shift register are latched
into SBUF.
The ninth data bit is latched into RB8 in SCON.
The receiver interrupt flag (RI) is set.
RI = 0 and either SM2 = 0 or SM2 = 1
The received stop bit = 1