ADUC832 Analog Devices, ADUC832 Datasheet - Page 34

• Manufacturer Part Number: ADUC832
• Description: Precision Analog Microcontroller: 1.3MIPS 8052 MCU + 62kB Flash + 8-Ch 12-Bit ADC + Dual 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC832

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 8
• Other: PWM

ADuC832
SPECIAL FUNCTION REGISTERS
All registers except the program counter and the four general-
purpose register banks reside in the special function register
(SFR) area. The SFR registers include control, configuration,
and data registers that provide an interface between the CPU
and other on-chip peripherals.
Figure 36 shows a full SFR memory map and SFR contents on
reset. Unoccupied SFR locations are shown dark-shaded in
Figure 36 (labeled not used). Unoccupied locations in the SFR
address space are not implemented, that is, no register exists at
SFR MAP KEY:
1
2
3
EFH
FFH
F7H
E7H
DFH
D7H
CFH
C7H
BFH
B7H
AFH
A7H
9FH
97H
8FH
87H
SFRs WHOSE ADDRESS ENDS IN 0H OR 8H ARE BIT ADDRESSABLE.
THE PRIMARY FUNCTION OF PORT1 IS AS AN ANALOG INPUT PORT; THEREFORE, TO ENABLE THE DIGITAL SECONDARY FUNCTIONS ON THESE
CALIBRATION COEFFICIENTS ARE PRECONFIGURED ON POWER-UP TO FACTORY CALIBRATED VALUES.
PORT PINS, WRITE A 0 TO THE CORRESPONDING PORT 1 SFR BIT.
PRE3
ADCI
MDO
SM0
ISPI
TF2
TF1
RD
CY
EA
0
0 F6H
0 EEH
0 E6H
0 DEH
0
0
0
0
1
0
0
1 96H
0
1 86H
1
FEH
D6H
CEH
C6H
BEH
B6H
AEH
9EH
8EH
A6H
WCOL
PADC
EADC
EXF2
PRE2
DMA
MDE
SM1
TR1
WR
AC
0
0 F5H
0
0 E5H
0 DDH
0
0
0
0
1
0
0
1 95H
0
1 85H
1
CCONV SCONV
FDH
EDH
D5H
CDH
C5H
BDH
B5H
ADH
9DH
8DH
A5H
RCLK
PRE1
MCO
SM2
SPE
PT2
ET2
TF0
F0
T1
0
0
0 F4H
0 ECH
0 E4H
0 DCH
0
0
0 C4H
0
1
1
0
1 94H
0
1 84H
FCH
D4H
CCH
BCH
B4H
ACH
A4H
9CH
8CH
TCLK
PRE0
SPIM
MDI
REN
RS1
TR0
PS
ES
T0
0
0 F3H
0 EBH
0 E3H
0 DBH
0
0
1
0
1
0
1 A3H
0
1 93H
0
1 83H
FBH
D3H
CBH
C3H
BBH
B3H
ABH
9BH
8BH
EXEN2
CPOL
WDIR
I2CM
INT1
CS3
RS0
PT1
ET1
TB8
IE1
SFR ADDRESS
DEFAULT VALUE
0
0 F2H
0 EAH
0 E2H
0 DAH
0
0
0
0
1
0
1 A2H
0
1 92H
0
1 82H
MNEMONIC
FAH
D2H
CAH
C2H
BAH
B2H
AAH
9AH
8AH
CPHA
I2CRS
WDS
INT0
CS2
RB8
TR2
PX1
EX1
OV
IT1
1
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
F9H
F1H
E9H
E1H
D9H
D1H
C9H
C1H
B9H
B1H
A9H
99H
91H
89H
A1H
81H
I2CTX
SPR1
CNT2
T2EX
WDE
CS1
PT0
TxD
ET0
Figure 36. Special Function Register Locations and Reset Values
IE0
F1
TI
THESE BITS ARE CONTAINED IN THIS BYTE.
0
0 F0H
0 E8H
0 E0H
0 D8H
0
0
0
0
1
0
1 A0H
0
1
0
1 80H
F8H
D0H
C8H
WDWR
C0H
B8H
B0H
A8H
98H
90H
88H
SPR0
CAP2
I2CI
CS0
RxD
PX0
EX0
IT0
89H
RI
T2
P
IE0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
88H
IT0
Rev. A | Page 34 of 92
0
C0H
D0H
C8H
B8H
B0H
A8H
D8H
A0H
98H
90H
88H
80H
F8H
F0H
E8H
E0H
ADCCON2
WDCON
I2CCON
SPICON
T2CON
SCON
TCON
ACC
PSW
P1
P3
P2
P0
IP
IE
B
1, 2
1
88H 00H
1
1
1
1
1
04H
00H
00H
FFH
00H
FFH
00H
FFH
00H
TCON
1
00H D9H
1
00H
00H
10H
00H B9H
FFH
00H
1
1
1
1
1
1
1
A9H
B1H
RESERVED
ADCDATAL
RESERVED
RESERVED
RESERVED
TIMECON
A1H
99H
89H
81H
F9H
F1H
RESERVED
NOT USED
ADCOFSL
PWM0L
that location. If an unoccupied location is read, an unspecified
value is returned. SFR locations reserved for on-chip testing are
shown lighter shaded in Figure 36 (labeled reserved) and should
not be accessed by user software. Sixteen of the SFR locations
are also bit addressable and denoted by Footnote 1 in Figure 36,
that is, the bit addressable SFRs are those whose address ends in
0H or 8H.
DAC0L
ECON
TMOD
SBUF
IEIP2
SP
A0H
00H
00H
00H
00H
00H
00H
00H
00H
07H
3
MNEMONIC
DEFAULT VALUE
SFR ADDRESS
DAH
D2H
CAH
C2H
B2H
A2H
9AH
8AH
82H
FAH
F2H
RESERVED
RESERVED
ADCDATAH
RESERVED
RESERVED
NOT USED
ADCOFSH
RCAP2L
HTHSEC
I2CDAT
DAC0H
PWM0H
CHIPID
DMAL
DPL
TL0
00H
20H
2XH
00H
00H
00H
00H
00H
00H
00H
00H
3
B3H
F3H
D3H
CBH
A3H
9BH
8BH
83H
FBH
RESERVED
RESERVED
RESERVED
RESERVED
ADCGAINL
RESERVED
NOT USED
RCAP2H
RESERVED
PWM1L
I2CADD
DAC1L
DMAH
DPH
SEC
TL1
00H
00H
00H
00H
00H
00H
55H
00H
00H
3
FCH
D4H
CCH
BCH
B4H
F4H
RESERVED
A4H
8CH
84H
ADCGAINH
RESERVED
RESERVED
RESERVED
NOT USED
NOT USED
EDATA1
RESERVED
DAC1H
PWM1H
DMAP
DPP
TH0
TL2
MIN
00H
00H
00H
00H
00H
00H
00H
00H
00H
3
9DH
FDH
F5H
RESERVED
RESERVED
RESERVED
CDH
RESERVED
BDH
A5H
8DH
RESERVED
DACCON
NOT USED
RESERVED
NOT USED
RESERVED
ADCCON3
EDATA2
HOUR
T3FD
TH2
TH1
04H
00H
00H
00H
00H
00H
00H
AEH
RESERVED
C6H
BEH
PWMCON
9EH
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
NOT USED
RESERVED
NOT USED
A6H
RESERVED
EDATA3
EADRL
T3CON
INTVAL
00H
00H
00H
00H
00H
ADCCON1
DFH
D7H
C7H
BFH
B7H
AFH
A7H
87H
RESERVED
F7H
EFH
RESERVED
RESERVED
NOT USED
NOT USED
RESERVED
PSMCON
PLLCON
EDATA4
CFG832
SPIDAT
EADRH
DPCON
PCON
SPH
00H
00H
00H
00H
00H
DEH
00H
00H
00H
53H