ADUC832 Analog Devices, ADUC832 Datasheet - Page 48

• Manufacturer Part Number: ADUC832
• Description: Precision Analog Microcontroller: 1.3MIPS 8052 MCU + 62kB Flash + 8-Ch 12-Bit ADC + Dual 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC832

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 8
• Other: PWM

ADuC832
USING THE FLASH/EE DATA MEMORY
The 4 kB of Flash/EE data memory is configured as 1024 pages,
each of four bytes. As with the other ADuC832 peripherals, the
interface to this memory space is via a group of registers
mapped in the SFR space. A group of four data registers
(EDATA1 to EDATA4) are used to hold the four bytes of data at
each page. The page is addressed via the EADRH and EADRL
registers. Finally, ECON is an 8-bit control register that may be
written with one of nine Flash/EE memory access commands to
trigger various read, write, erase, and verify functions.
A block diagram of the SFR interface to the Flash/EE data
memory array is shown in Figure 50.
ECON—FLASH/EE MEMORY CONTROL SFR
Programming of either the Flash/EE data memory or the
Flash/EE program memory is done through the Flash/EE
memory control SFR (ECON). This SFR allows the user to read,
write, erase, or verify the 4 kB of Flash/EE data memory or the
56 kB of Flash/EE program memory.
Table 21. ECON—Flash/EE Memory Commands
ECON Value
01H READPAGE
02H WRITEPAGE
03H
04H VERIFYPAGE
05H ERASEPAGE
06H ERASEALL
81H READBYTE
82H WRITEBYTE
0FH EXULOAD
F0H ULOAD
1
Register EADRH and EADRL form the full address, EADRH/L.
Command Description (Normal Mode)
(Power-On Default)
Results in four bytes in the Flash/EE data memory,
addressed by the page address EADRH/L, being read into
EDATA1 to EDATA4.
Results in four bytes in EDATA1 to EDATA4 being written to
the Flash/EE data memory at the page address given by
EADRH/L
bytes in the page being addressed must be pre-erased.
Reserved command.
Verifies if the data in EDATA[1:4] is contained in the page
address given by EADRH/L. A subsequent read of the
ECON SFR results in a 0 being read if the verification is
valid, or a nonzero value being read to indicate an invalid
verification.
Results in the erase of the 4-byte page of Flash/EE data
memory addressed by the Page Address EADRH/L.
Results in the erase of entire 4 kB of Flash/EE data
memory.
Results in the byte in the Flash/EE data memory,
addressed by the Byte Address EADRH/L, being read into
EDATA1 (0 ≤ EADRH/L ≤ 0FFFH).
Results in the byte in EDATA1 being written into Flash/EE
data memory, at the byte address EADRH/L.
Leaves the ECON instructions to operate on the Flash/EE
data memory.
Enters ULOAD mode, directing subsequent ECON
instructions to operate on the Flash/EE program memory.
1
(0 ≤ EADRH/L < 0400H). Note that the four
Rev. A | Page 48 of 92
ARE GIVEN IN
ADDRESSES
BRACKETS
BYTE
3FEH
3FFH
03H
02H
01H
00H
Figure 50. Flash/EE Data Memory Control and Configuration
Command Description (ULOAD Mode)
Not implemented. Use the MOVC instruction.
Results in Byte 0 to Byte 255 of internal XRAM being
written to the 256 bytes of Flash/EE program memory at
the page address given by EADRH (0 ≤ EADRH < E0H).
Note that the 256 bytes in the page being addressed
must be pre-erased.
Reserved command.
Not implemented. Use the MOVC and MOVX instructions
to verify the WRITE in software.
Results in the 64-byte page of Flash/EE program memory,
addressed by the Byte Address EADRH/L being erased.
EADRL can equal any of 64 locations within the page.
A new page starts whenever EADRL is equal to 00H, 40H,
80H, or C0H.
Results in the erase of the entire 56 kB of ULOAD Flash/EE
program memory.
Not implemented. Use the MOVC command.
Results in the byte in EDATA1 being written into Flash/EE
program memory, at the Byte Address EADRH/L (0 ≤
EADRH/L ≤ DFFFH).
Enters normal mode directing subsequent ECON
instructions to operate on the Flash/EE data memory.
Leaves the ECON instructions to operate on the Flash/EE
program memory.
(0FFCH)
(0FF8H)
(000CH)
(0008H)
(0004H)
BYTE 1
BYTE 1
BYTE 1
BYTE 1
(0000H)
BYTE 1
BYTE 1
(0FFDH)
(0FF9H)
(000DH)
(0009H)
(0005H)
BYTE 2
BYTE 2
BYTE 2
BYTE 2
BYTE 2
BYTE 2
(0001H)
(0FFAH)
(0FFEH)
BYTE 3
BYTE 3
(000EH)
(000AH)
(0006H)
(0002H)
BYTE 3
BYTE 3
BYTE 3
BYTE 3
(0FFFH)
BYTE 4
(0FFBH)
(000FH)
(000BH)
(0007H)
(0003H)
BYTE 4
BYTE 4
BYTE 4
BYTE 4
BYTE 4