ADUC832 Analog Devices, ADUC832 Datasheet - Page 31

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ADUC832

Manufacturer Part Number
ADUC832
Description
Precision Analog Microcontroller: 1.3MIPS 8052 MCU + 62kB Flash + 8-Ch 12-Bit ADC + Dual 12-Bit DAC
Manufacturer
Analog Devices
Datasheet

Specifications of ADUC832

Mcu Core
8052
Mcu Speed (mips)
1.3
Sram (bytes)
2304Bytes
Gpio Pins
34
Adc # Channels
8
Other
PWM

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MEMORY ORGANIZATION
The ADuC832 contains four different memory blocks:
FLASH/EE PROGRAM MEMORY
The ADuC832 provides 62 kB of Flash/EE program memory to
run user code. The user can choose to run code from this
internal memory or from an external program memory.
If the user applies power or resets the device while the EA pin
is pulled low, the part executes code from the external program
space; otherwise, the part defaults to code execution from its inter-
nal 62 kB of Flash/EE program memory. Unlike the ADuC812,
where code execution can overflow from the internal code space to
external code space once the PC becomes greater than 1FFFH,
the ADuC832 does not support the rollover from F7FFH in
internal code space to F800H in external code space. Instead,
the 2048 bytes between F800H and FFFFH appear as NOP
instructions to user code.
This internal code space can be downloaded via the UART
serial port while the device is in-circuit. During runtime, 56 kB
of the program memory can be reprogrammed; thus the code
space can be upgraded in the field using a user defined proto-
col, or it can be used as a data memory (for more details, see
the Using the Flash/EE Program Memory section).
FLASH/EE DATA MEMORY
4 kB of Flash/EE data memory are available to the user and can
be accessed indirectly via a group of control registers mapped
into the Special Function Register (SFR) area. Access to the
Flash/EE data memory is discussed in detail in the Using the
Flash/EE Data Memory section.
GENERAL-PURPOSE RAM
The general-purpose RAM is divided into two separate memo-
ries, the upper and the lower 128 bytes of RAM. The lower
128 bytes of RAM can be accessed through direct or indirect
addressing. The upper 128 bytes of RAM can only be accessed
through indirect addressing because it shares the same address
space as the SFR space, which can only be accessed through
direct addressing.
The lower 128 bytes of internal data memory are mapped as shown
in Figure 32. The lowest 32 bytes are grouped into four banks of
eight registers addressed as R0 through R7. The next 16 bytes
(128 bits), above the register banks, form a block of bit addressable
memory space at Address 20H through Address 2FH. The stack
can be located anywhere in the internal memory address space,
and the stack depth can be expanded up to 2048 bytes.
62 kB of on-chip Flash/EE program memory
4 kB of on-chip Flash/EE data memory
256 bytes of general-purpose RAM
2 kB of internal XRAM
Rev. A | Page 31 of 92
A reset initializes the stack pointer to Location 07H and incre-
ments it once before loading the stack to start from Location
08H, which is also the first register (R0) of Register Bank 1.
Thus, if using more than one register bank, the stack pointer
should be initialized to an area of RAM not used for data
storage.
The ADuC832 contains 2048 bytes of internal XRAM,
1792 bytes of which can be configured to be used as an
extended 11-bit stack pointer.
By default, the stack operates exactly like an 8052 in that it rolls
over from FFH to 00H in the general-purpose RAM. On the
ADuC832, however, it is possible (by setting CFG832[7]) to
enable the 11-bit extended stack pointer. In this case, the stack
rolls over from 00FFH in RAM to 0100H in XRAM.
The 11-bit stack pointer is visible in the SP and SPH SFRs. The
SP SFR is located at 81H as with a standard 8052. The SPH SFR
is located at B7H. The three LSBs of this SFR contain the three
extra bits necessary to extend the 8-bit stack pointer into an
11-bit stack pointer.
BITS IN PSW
SELECTED
BANKS
VIA
Figure 32. Lower 128 Bytes of Internal Data Memory
CFG832[7] = 0
10
11
01
00
Figure 33. Extended Stack Pointer Operation
FFH
00H
30H
20H
18H
10H
08H
00H
ON-CHIP DATA
256 BYTES OF
(DATA +
STACK)
RAM
CFG832[7] = 1
07FFH
100H
00H
7FH
2FH
1FH
17H
0FH
07H
(DATA + STACK
ON-CHIP XRAM
ON-CHIP XRAM
FOR EXSP = 1,
FOR EXSP = 0)
(DATA ONLY)
UPPER 1792
DATA ONLY
LOWER 256
BYTES OF
BYTES OF
GENERAL-PURPOSE
AREA
BIT-ADDRESSABLE
(BIT ADDRESSES)
FOUR BANKS OF EIGHT
REGISTERS
R0 TO R7
RESET VALUE OF
STACK POINTER
ADuC832

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