ADUC832 Analog Devices, ADUC832 Datasheet - Page 68

• Manufacturer Part Number: ADUC832
• Description: Precision Analog Microcontroller: 1.3MIPS 8052 MCU + 62kB Flash + 8-Ch 12-Bit ADC + Dual 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC832

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 8
• Other: PWM

ADuC832
them drive a logic low output voltage (V
sinking 1.6 mA.
P2.6 and P2.7 can also be used as PWM outputs. If they are
selected as the PWM outputs via the CFG832 SFR, the PWM
outputs overwrite anything written to P2.6 or P2.7.
PORT 3
Port 3 is a bidirectional port with internal pull-ups directly
controlled via the P3 SFR. Port 3 pins that have 1s written to
them are pulled high by the internal pull-ups and, in that state,
can be used as inputs. As inputs, Port 3 pins pulled externally
low source current because of the internal pull-ups. Port 3 pins
with 0s written to them drive a logic low output voltage (V
and are capable of sinking 4 mA.
Port 3 pins also have various secondary functions described in
Table 35. The alternate functions of Port 3 pins can only be
activated if the corresponding bit latch in the P3 SFR contains a 1.
Otherwise, the port pin is stuck at 0.
Table 35. Port 3, Alternate Pin Functions
Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.3 and P3.4 can also be used as PWM outputs. If they are
selected as the PWM outputs via the CFG832 SFR, the PWM
outputs overwrite anything written to P3.4 or P3.3.
TO LATCH
INTERNAL
LATCH
FROM
PORT
LATCH
WRITE
READ
READ
BUS
PIN
Q
Alternate Function
RxD (UART input pin or serial data I/O in Mode 0)
TxD (UART output pin or serial clock output in Mode 0)
INT0 (External Interrupt 0)
INT1 (External Interrupt 1) or PWM1/MISO
T0 (Timer/Counter 0 external input), PWMC, PWM0, or
EXTCLK
T1 (Timer/Counter 1 external input) or CONVST
WR (external data memory write strobe)
RD (external data memory read strobe)
DELAY
2 CLK
Figure 69. Internal Pull-Up Configuration
Figure 68. Port 2 Bit Latch and I/O Buffer
LATCH
CL
D
Q
Q
ADDR
*SEE FIGURE 69 FOR
DETAILS OF INTERNAL PULL-UP
CONTROL
Q4
Q1
DV
DD
Q2
OL
DV
) and are capable of
DD
DV
DD
Q3
DV
DV
DD
DD
INTERNAL
PULL-UP*
P2.x
PIN
P2.x
PIN
OL
)
Rev. A | Page 68 of 92
ADDITIONAL DIGITAL I/O
In addition to the port pins, the dedicated SPI/I
(SCLOCK and SDATA/MOSI) also feature both input and
output functions. Their equivalent I/O architectures are
illustrated in Figure 71 and Figure 73, respectively, for SPI
operation and in Figure 72 and Figure 74 for I
Notice that in I
up FET (Q1) is disabled, leaving only a weak pull-up (Q2)
present. By contrast, in SPI mode (SPE = 1) the strong pull-up
FET (Q1) is controlled directly by SPI hardware, giving the pin
push-pull capability.
In I
operate in parallel to provide an extra 60% or 70% of current
sinking capability. In SPI mode, however, (SPE = 1) only one of
the pull-down FETs (Q3) operates on each pin, resulting in sink
capabilities identical to that of Port 0 and Port 2 pins. On the
input path of SCLOCK, notice that a Schmitt trigger conditions
the signal going to the SPI hardware to prevent false triggers
(double triggers) on slow incoming edges. For incoming signals
from the SCLOCK and SDATA pins going to I
conditions the signals in order to reject glitches of up to 50 ns in
duration.
Notice also that direct access to the SCLOCK and SDATA/MOSI
pins is afforded through the SFR interface in I
Therefore, if the SPI or I
pins can be used to give additional high current digital outputs.
INTERNAL
TO LATCH
(MASTER/SLAVE)
2
HARDWARE SPI
C mode (SPE = 0), two pull-down FETs (Q3 and Q4)
LATCH
WRITE
READ
READ
BUS
Figure 71. SCLOCK Pin I/O Functional Equivalent in SPI Mode
PIN
SPE = 1 (SPI ENABLE)
2
Figure 70. Port 3 Bit Latch and I/O Buffer
C mode (SPE, SPICON[5] = 0), the strong pull-
LATCH
D
CL
Q
Q
SCHMITT
TRIGGER
2
ALTERNATE
ALTERNATE
C functions are not used, these two
FUNCTION
FUNCTION
OUTPUT
INPUT
Q1
Q3
DV
DD
DV
DD
Q2 (OFF)
Q4 (OFF)
INTERNAL
PULL-UP*
*SEE FIGURE 69
FOR DETAILS OF
INTERNAL PULL-UP
2
C hardware, a filter
2
2
C operation.
C master mode.
2
C pins
P3.x
PIN
SCLOCK
PIN