ADUC832 Analog Devices, ADUC832 Datasheet - Page 51

• Manufacturer Part Number: ADUC832
• Description: Precision Analog Microcontroller: 1.3MIPS 8052 MCU + 62kB Flash + 8-Ch 12-Bit ADC + Dual 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC832

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 8
• Other: PWM

USER INTERFACE TO OTHER ON-CHIP ADUC832 PERIPHERALS
The following section gives a brief overview of the various
peripherals also available on-chip. A summary of the SFRs used
to control and configure these peripherals is also given.
DAC
The ADuC832 incorporates two 12-bit voltage output DACs on
chip. Each DAC has a rail-to-rail voltage output buffer capable
of driving 10 kΩ/100 pF. Each has two selectable ranges, 0 V to
V
Each can operate in 12-bit or 8-bit mode. Both DACs share a
control register, DACCON, and four data registers, DAC1H,
DAC1L, DAC0H, and DAC0L. Note that in 12-bit asynchron-
ous mode, the DAC voltage output is updated as soon as the
DACL data SFR has been written; therefore, the DAC data
registers should be updated as DACH first, followed by DACL.
Note that for correct DAC operation on the 0 V to V
the ADC must be switched on. This results in the DAC using
the correct reference value.
DACCON (DAC Control Register)
SFR Address:
Power-On Default Value:
Bit Addressable:
Table 25. DACCON SFR Bit Designations
Bit
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
REF
(the internal band gap 2.5 V reference) and 0 V to AV
Name
Mode
RNG1
RNG0
CLR1
CLR0
SYNC
PD1
PD0
The DAC MODE bit sets the overriding operating mode for both DACs.
Set to 1 = 8-bit mode (write eight bits to DACxL SFR).
Set to 0 = 12-bit mode.
DAC1 range select bit.
Set to 1 = DAC1 range 0 V − V
Set to 0 = DAC1 range 0 V − V
DAC0 range select bit.
Set to 1 = DAC0 range 0 V − V
Set to 0 = DAC0 range 0 V − V
DAC1 clear bit.
Set to 0 = DAC1 output forced to 0 V.
Set to 1 = DAC1 output normal.
DAC0 clear bit. Set to 0 = DAC1 Output Forced to 0 V. Set to 1 = DAC1 output normal.
DAC0/DAC1 update synchronization bit.
When set to 1, the DAC outputs update as soon as DACxL SFRs are written. The user can simultaneously update
both DACs by first updating the DACxL/DACxH SFRs while SYNC is 0. Both DACs then update simultaneously
when the SYNC bit is set to 1.
DAC1 Power-down bit.
Set to 1 = power on DAC1.
Set to 0 = power off DAC1.
DAC0 Power-Down Bit.
Set to 1 = power on DAC0.
Set to 0 = power off DAC0.
Description
FDH
04H
No
REF
range,
DD
REF
DD
REF
.
.
DD
.
.
Rev. A | Page 51 of 92
.
DACxH/DACxL (DAC Data Registers)
Function:
SFR Address:
Power-On Default
Bit Addressable:
The 12-bit DAC data should be written into DACxH/DACxL
right-justified such that DACxL contains the lower eight bits,
and the lower nibble of DACxH contains the upper four bits.
Value:
DAC data registers, written by user to
update the DAC output
DAC0L (DAC0 data low byte) = F9H;
DAC1L (DAC1 data low byte) = FBH
DAC0H (DAC0 data high byte) = FAH;
DAC1H (DAC1 data high byte) = FCH
00H (all four registers)
No (all four registers)
ADuC832