ADUC832 Analog Devices, ADUC832 Datasheet - Page 61

• Manufacturer Part Number: ADUC832
• Description: Precision Analog Microcontroller: 1.3MIPS 8052 MCU + 62kB Flash + 8-Ch 12-Bit ADC + Dual 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC832

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 8
• Other: PWM

OVERVIEW
The main features of the MicroConverter I
•
•
•
SOFTWARE MASTER MODE
The ADuC832 can be used as an I
configuring the I
software to output the data bit by bit. This is referred to as a
software master. Master mode is enabled by setting the I2CM
bit in the I2CCON register.
To transmit data on the SDATA line, MDE must be set to enable
the output driver on the SDATA pin. If MDE is set, then the
SDATA pin is pulled high or low depending on whether the
MDO bit is set or cleared. MCO controls the SCLOCK pin and
is always configured as an output in master mode. In master mode,
the SCLOCK pin is pulled high or low depending on the
whether MCO is set or cleared.
To receive data, MDE must be cleared to disable the output
driver on SDATA. Software must provide the clocks by toggling
the MCO bit and reading the SDATA pin via the MDI bit. If
MDE is cleared, MDI can be used to read the SDATA pin. The
value of the SDATA pin is latched into MDI on a rising edge of
SCLOCK. MDI is set if the SDATA pin was high on the last
rising edge of SCLOCK. MDI is cleared if the SDATA pin was
low on the last rising edge of SCLOCK.
Software must control MDO, MCO, and MDE appropriately to
generate the start condition, slave address, acknowledge bits,
data bytes, and stop conditions appropriately. These functions
are provided in Technical Note uC001.
HARDWARE SLAVE MODE
After reset, the ADuC832 defaults to hardware slave mode.
The I
Slave mode is enabled by clearing the I2CM bit in I2CCON.
The ADuC832 has a full hardware slave. In slave mode, the I
address is stored in the I2CADD register. Data received or to be
transmitted is stored in the I2CDAT register.
Only two bus lines are required; a serial data line (SDATA)
and a serial clock line (SCLOCK).
An I
devices. Because each slave device has a unique 7-bit
address, single master/slave relationships can exist at all
times even in a multislave environment (Figure 64).
On-chip filtering rejects <50 ns spikes on the SDATA and
the SCLOCK lines to preserve data integrity.
2
C interface is enabled by clearing the SPE bit in SPICON.
2
C master can communicate with multiple slave
MASTER
2
C peripheral in master mode and writing
I
2
C
Figure 64. Typical I
DV
DD
2
C master device by
2
C System
SLAVE 1
SLAVE 2
I
I
2
2
2
C
C
C interface are:
Rev. A | Page 61 of 92
2
C
Once enabled in I
start condition. If the ADuC832 detects a valid start condition,
followed by a valid address, followed by the R/ W bit, the I2CI
interrupt bit is automatically set by hardware.
The I
has preconfigured the I
SFR, as well as the global interrupt bit (EA) in the IE SFR.
; Enabling I
MOV IEIP2,#01H
SETB EA
On the ADuC832, an autoclear of the I2CI bit is implemented
so this bit is cleared automatically on a read or write access to
the I2CDAT SFR.
MOV
MOV
If for any reason the user tries to clear the interrupt more than
once, that is, access the data SFR more than once per interrupt,
then the I
using the I2CRS bit.
The user can choose to poll the I2CI bit or enable the interrupt.
In the case of the interrupt, the PC counter vectors to 003BH at
the end of each complete byte. For the first byte, when the user
reaches the I2CI interrupt service routine (ISR), the 7-bit
address and the R/ W bit appear in the I2CDAT SFR.
The I2CTX bit contains the R/ W bit sent from the master. If
I2CTX is set, then the master waits to receive a byte. Thus the
slave transmits data by writing to the I2CDAT register. If I2CTX
is cleared, the master transmits a byte. Therefore, the slave receives
a serial byte. The software can check the state of I2CTX to
determine whether it should write to or read from I2CDAT.
Once the ADuC832 has received a valid address, the hardware
hold SCLOCK low until the I2CI bit is cleared by software. This
allows the master to wait for the slave to be ready before
transmitting the clocks for the next byte.
The I2CI interrupt bit is set every time a complete data byte is
received or transmitted, provided it is followed by a valid ACK.
If the byte is followed by a NACK, an interrupt is not generated.
The ADuC832 continues to issue interrupts for each complete
data byte transferred until a stop condition is received or the
interface is reset.
When a stop condition is received, the interface resets to a state
where it is waiting to be addressed (idle). Similarly, if the
interface receives a NACK at the end of a sequence, it also returns
to the default idle state. The I2CRS bit can be used to reset the
I
the default idle state.
It should be noted that there is no way (in hardware) to distinguish
between an interrupt generated by a received start plus valid
address and an interrupt generated by a received data byte. User
software must be used to distinguish between these interrupts.
2
C interface. This bit can be used to force the interface back to
2
C peripheral only generates a core interrupt if the user
I2CDAT, A
A, I2CDAT
2
C controller stops. The interface then must be reset
2
2
C Interrupts for the ADuC832
C slave mode, the slave controller waits for a
2
C interrupt enable bit (ESI) in the IEIP2
; enable I
; I2CI autocleared
; I2CI autocleared
2
C interrupt
ADuC832