ADUC832 Analog Devices, ADUC832 Datasheet - Page 50

• Manufacturer Part Number: ADUC832
• Description: Precision Analog Microcontroller: 1.3MIPS 8052 MCU + 62kB Flash + 8-Ch 12-Bit ADC + Dual 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC832

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 8
• Other: PWM

ADuC832
ADUC832 CONFIGURATION SFR (CFG832)
The CFG832 SFR contains the necessary bits to configure the
internal XRAM, external clock select, PWM output selection,
DAC buffer, and the extended SP. By default, it configures the
user into 8051 mode; that is, extended SP is disabled and the
internal XRAM is disabled.
Table 24. CFG832 SFR Bit Designations
Bit
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Name
EXSP
PWPO
DBUF
EXTCLK
RSVD
RSVD
RSVD
XRAMEN
Reserved. This bit should always contain 0.
Reserved. This bit should always contain 0.
Reserved. This bit should always contain 0.
Description
Extended SP enable.
When set to 1 by the user, the stack rolls over from SPH/SP = 00FFH to SPH/SP = 0100H.
When set to 0 by the user, the stack rolls over from SP = FFH to SP = 00H.
PWM pinout selection.
When set to 1 by the user, the PWM output pins are selected as P3.4 and P3.3.
When set to 0 by the user, the PWM output pins are selected as P2.6 and P2.7.
DAC output buffer.
When set to 1 by the user, the DAC output buffer is bypassed.
When set to 0 by the user, the DAC output buffer is enabled.
Set by the user to 1 to select an external clock input on P3.4.
Set by the user to 0 to use the internal PLL clock.
XRAM enable bit.
When set to 1 by the user, the internal XRAM is mapped into the lower 2 kB of the external address space.
When set to 0 by the user, the internal XRAM is not accessible and the external data memory is mapped into the lower
2 kB of external data memory.
Rev. A | Page 50 of 92
CFG832 (ADuC832 Configuration SFR)
SFR Address:
Power-On Default Value:
Bit Addressable:
AFH
00H
No