ADUC832 Analog Devices, ADUC832 Datasheet - Page 52

• Manufacturer Part Number: ADUC832
• Description: Precision Analog Microcontroller: 1.3MIPS 8052 MCU + 62kB Flash + 8-Ch 12-Bit ADC + Dual 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC832

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 8
• Other: PWM

ADuC832
USING THE DAC
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier, the functional equivalent
of which is illustrated in Figure 51. Details of the actual DAC
architecture can be found in U.S. Patent Number 5,969,657.
Features of this architecture include inherent guaranteed
monotonicity and excellent differential linearity.
As illustrated in Figure 51, the reference source for each DAC is
user selectable in software. It can be either AV
to AV
V to the voltage at the AV
output transfer function spans from 0 V to the internal V
if an external reference is applied, the voltage at the V
The DAC output buffer amplifier features a true rail-to-rail
output stage implementation. This means that, unloaded, each
output is capable of swinging to within less than 100 mV of both
AV
(when driving a 10 kΩ resistive load to ground) is guaranteed
through the full transfer function except Code 0 to Code 100,
and, in 0 V to AV
degradation near ground and AV
the output amplifier, and a general representation of its effects
(neglecting offset and gain error) is illustrated in Figure 52. The
dotted line in Figure 52 indicates the ideal transfer function,
and the solid line represents what the transfer function may
look like with endpoint nonlinearities due to saturation of the
output amplifier. Note that Figure 52 represents a transfer
function in 0 V to AV
V
portion of the transfer function follows the ideal line to the end
(V
linearity errors.
REF
REF
DD
< AV
and ground. Moreover, the DAC’s linearity specification
in this case, not AV
DD
mode, the DAC output transfer function spans from 0
AV
V
DD
REF
Figure 51. Resistor String DAC Functional Equivalent
DD
), the lower nonlinearity is similar, but the upper
DD
mode only, Code 3995 to Code 4095. Linearity
R
R
R
R
R
DD
mode only. In 0 V to V
ADuC832
DD
DD
), showing no signs of endpoint
pin. In 0 V to V
DD
(FROM MCU)
is caused by saturation of
DISABLE
OUTPUT
BUFFER
HIGH Z
REF
DD
mode, the DAC
REF
or V
DAC0
mode (with
REF
REF
. In 0 V
pin.
REF
or,
Rev. A | Page 52 of
The endpoint nonlinearities conceptually illustrated in Figure 52
become worse as a function of output loading. Most of the
ADuC832 specifications assume a 10 kΩ resistive load to
ground at the DAC output. As the output is forced to source or
sink more current, the nonlinear regions at the top or bottom
(respectively) of Figure 52 become larger. With larger current
demands, this can significantly limit output voltage swing.
Figure 53 and Figure 54 illustrate this behavior. It should be
noted that the upper trace in each of these figures is only valid
for an output range selection of 0 V to AV
mode, DAC loading does not cause high-side voltage drops as
long as the reference voltage remains below the upper trace in
the corresponding figure. For example, if AV
2.5 V, the high-side voltage is not affected by loads less than
5 mA. However, around 7 mA, the upper curve in Figure 54
drops below 2.5 V (V
currents, the output is not capable of reaching V
AV
AV
92
DD
DD
Figure 53. Source and Sink Current Capability with V
–100mV
–50mV
100mV
Figure 52. Endpoint Nonlinearities Due to Amplifier Saturation
50mV
AV
5
4
3
2
1
0
0mV
0
DD
000H
SOURCE/SINK CURRENT (mA)
REF
), indicating that, at these higher
5
DAC LOADED WITH 0FFFH
DAC LOADED WITH 0000H
10
DD
. In 0 V to V
DD
= 3 V and V
REF
REF
= AV
.
DD
15
= 5 V
REF
FFFH
REF
=