ADUC832 Analog Devices, ADUC832 Datasheet - Page 60

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ADUC832

Manufacturer Part Number
ADUC832
Description
Precision Analog Microcontroller: 1.3MIPS 8052 MCU + 62kB Flash + 8-Ch 12-Bit ADC + Dual 12-Bit DAC
Manufacturer
Analog Devices
Datasheet

Specifications of ADUC832

Mcu Core
8052
Mcu Speed (mips)
1.3
Sram (bytes)
2304Bytes
Gpio Pins
34
Adc # Channels
8
Other
PWM

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ADuC832
I
The ADuC832 supports a fully licensed I
I
ware master. SDATA is the data I/O pin and SCLOCK is the
serial clock. These two pins are shared with the MOSI and
SCLOCK pins of the on-chip SPI interface. Therefore, the user
can only enable one interface or the other at any given time
(see SPE in SPICON in Table 28). The uC001 Technical Note,
MicroConverter® I
tion of this interface as implemented, and is available from the
MicroConverter website at www.analog.com/microconverters.
I
Three SFRs are used to control the I
described in the following sections.
I2CCON (I
SFR Address:
Power-On Default Value:
Bit Addressable:
Table 29. I2CCON SFR Bit Designations
Bit
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
2
2
2
C interface is implemented as a full hardware slave and soft-
C INTERFACE SFRs
C-COMPATIBLE INTERFACE
Name
MDO
MDE
MCO
MDI
I2CM
I2CRS
I2CTX
I2CI
2
Control Register)
Description
I
in software. Data written to this bit is output on the SDATA pin if the data output enable (MDE) bit is set.
I
Cleared by the user to enable SDATA pin as an input (Rx).
I
in software. Data written to this bit is output on the SCLOCK pin.
I
software. Data on the SDATA pin is latched into this bit on SCLOCK if the data output enable (MDE) bit is 0.
I
mode.
I
I
MicroConverter if the interface is receiving.
I
automatically when user code reads the I2CDAT SFR (see the I2CADD (I2C Address Register) section).
2
2
2
2
2
2
2
2
C software master data output bit (master mode only). This data bit is used to implement a master I
C software master data output enable bit (master mode only). Set by user to enable the SDATA pin as an output (Tx).
C software master clock output bit (master mode only). This data bit is used to implement a master I
C software master data input bit (master mode only). This data bit is used to implement a master I
C master/slave mode bit set by user to enable I
C reset bit (slave mode only). Set by user to reset the I
C direction transfer bit (slave mode only). Set by the MicroConverter if the interface is transmitting. Cleared by the
C interrupt bit (slave mode only). Set by the MicroConverter after a byte has been transmitted or received. Cleared
2
C® Compatible Interface, describes the opera-
E8H
00H
Yes
2
C interface. These are
2
C serial interface. The
Rev. A | Page 60 of 92
2
C software master mode. Cleared by user to enable I
2
C interface. Cleared by user code for normal I
I2CADD (I
SFR Address:
Power-On Default Value:
Bit Addressable:
The I2CADD SFR holds the I
It can be overwritten by user code. Technical Note uC001 at
www.analog.com/microconverters describes the format of the
I
I2CDAT (I
SFR Address:
Power-On Default Value:
Bit Addressable:
The I2CDAT SFR is written by the user to transmit data over
the I
by the I
pending I
software should only access I2CDAT once per interrupt cycle.
2
C standard 7-bit address in detail.
2
C interface or read by user code to read data just received
2
C interface. Accessing I2CDAT automatically clears any
2
C interrupt and the I2CI bit in the I2CCON SFR. User
2
2
C Data Register)
C Address Register)
9BH
55H
No
9AH
00H
No
2
C peripheral address for the part.
2
C receiver interface in
2
2
C transmitter interface
2
2
C operation.
C hardware slave
C transmitter interface

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