ADUC832 Analog Devices, ADUC832 Datasheet - Page 63

• Manufacturer Part Number: ADUC832
• Description: Precision Analog Microcontroller: 1.3MIPS 8052 MCU + 62kB Flash + 8-Ch 12-Bit ADC + Dual 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC832

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 8
• Other: PWM

POWER SUPPLY MONITOR
As its name suggests, the power supply monitor, once enabled,
monitors the DV
any of the supply pins drop below one of four user-selectable
voltage trip points from 2.63 V to 4.37 V. For correct operation
of the power supply monitor function, AV
or greater than 2.7 V. The monitor function is controlled via
the PSMCON SFR. If enabled via the IEIP2 SFR, the monitor
interrupts the core using the PSMI bit in the PSMCON SFR.
This bit is not cleared until the failing power supply has returned
above the trip point for at least 250 ms. This monitor function
allows the user to save working registers to avoid possible data
loss due to the low supply condition, and ensures that normal
Table 31. PSMCON SFR Bit Designations
Bit
[7]
[6]
[5]
[4:3]
[2]
[1]
[0]
Name
Reserved
CMPD
PSMI
TPD[1:0]
Reserved
Reserved
PSMEN
DD
Description
Reserved.
DV
This is a read-only bit and directly reflects the state of the DV
Read 1 indicates the DV
Read 0 indicates the DV
Power supply monitor interrupt bit.
This bit is set high by the MicroConverter if CMPD is low, indicating low analog or digital supply. The PSMI bit can be
used to interrupt the processor. Once CMPD returns (and remains) high, a 250 ms counter is started. When this counter
times out, the PSMI interrupt is cleared. PSMI can also be written by the user. However, if either comparator output is
low, it is not possible for the user to clear PSMI.
DV
TPD1
0
0
1
1
Reserved.
Reserved.
Power supply monitor enable bit. Set to 1 by the user to enable the power supply monitor circuit. Cleared to 0 by the
user to disable the power supply monitor circuit.
supply on the ADuC832. It indicates when
DD
DD
comparator bit.
trip point selection bits. These bits select the DV
DD
DD
DD
TPD0
0
1
0
1
must be equal to
supply is above its selected trip point.
supply is below its selected trip point.
Rev. A | Page 63 of 92
Selected DV
4.37
3.08
2.93
2.63
DD
code execution does not resume until a safe supply level has
been well established. The supply monitor is also protected
against spurious glitches triggering the interrupt circuit.
PSMCON (POWER SUPPLY MONITOR CONTROL
REGISTER )
SFR Address:
Power-On Default Value:
Bit Addressable :
trip point voltage as follows:
DD
DD
comparator.
Trip Point (V)
DFH
DEH
No
ADuC832