ADUC832 Analog Devices, ADUC832 Datasheet - Page 84

• Manufacturer Part Number: ADUC832
• Description: Precision Analog Microcontroller: 1.3MIPS 8052 MCU + 62kB Flash + 8-Ch 12-Bit ADC + Dual 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC832

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 8
• Other: PWM

ADuC832
POWER CONSUMPTION
The currents consumed by the various sections of the ADuC832
are shown in Table 50. The core values given represent the
current drawn by DV
reference) are pulled by the AV
software when not in use. The other on-chip peripherals (for
example, watchdog timer and power supply monitor) consume
negligible current and are therefore included with the core
operating current. The user must add any currents sourced by
the parallel and serial I/O pins and by the DAC to determine
the total current needed at the ADuC832 supply pins. Also,
current drawn from the DV
imately 10 mA during Flash/EE erase and program cycles.
Table 50. Typical I
Core/Peripherals
Core, Normal Mode
Core, Idle Mode
ADC
DAC (Each)
Voltage Reference
Because the operating DV
clock speed, the expressions for core supply current in Table 50
are given as functions of M
value for M
the core at that oscillator frequency. Because the ADC and
DACs can be enabled or disabled in software, add only the
currents from the peripherals that are expected to be used. Do
not forget to include current sourced by I/O pins, serial port
pins, and DAC outputs, plus the additional current drawn
during Flash/EE erase and program cycles. A software switch
allows the chip to be switched from normal mode into idle
mode, and into full power-down mode. The following sections
provide brief descriptions of power-down and idle modes.
POWER SAVING MODES
In idle mode, the oscillator continues to run but the core clock
generated from the PLL is halted. The on-chip peripherals
continue to receive the clock, and remain functional. The CPU
status is preserved with the stack pointer and program counter,
and all other internal registers maintain their data during idle
mode. Port pins and DAC output pins retain their states in this
mode. The chip recovers from idle mode upon receiving any
enabled interrupt, or upon receiving a hardware reset.
In full power-down mode, both the PLL and the clock to the
core are stopped. The on-chip oscillator can be halted or can
continue to oscillate depending on the state of the oscillator
power-down bit (OSC_PD) in the PLLCON SFR. The TIC,
being driven directly from the oscillator, can also be enabled
during power-down. All other on-chip peripherals, however, are
shut down. Port pins retain their logic levels in this mode, but
the DAC output goes to a high impedance state (three-state).
CLK
in hertz to determine the current consumed by
DD
DD
of Core and Peripherals
V
(1.6 nA × M
6 mA
(0.75 nA × M
5 mA
1.3 mA
250 μA
200 μA
, and the rest (ADC, DAC, voltage
DD
DD
= 5 V
CLK
DD
current is primarily a function of
, the core clock frequency. Use a
supply increases by approx-
DD
pin and can be disabled in
CLK
CLK
) +
) +
V
(0.8 nA × M
3 mA
(0.25 nA × M
3 mA
1.0 mA
200 μA
150 μA
DD
= 3 V
CLK
CLK
) +
) +
Rev. A | Page 84 of 92
During full power-down mode, the ADuC832 consumes a total
of approximately 20 μA. There are five ways of terminating
power-down mode.
Asserting the RESET Pin
Asserting the RESET pin returns the part to normal mode. All
registers are set to their default state and program execution
starts at the reset vector when the RESET pin is deasserted.
Cycling Power
All registers are set to their default state and program execution
starts at the reset vector approximately 128 ms later.
Time Interval Counter (TIC) Interrupt
Power-down mode is terminated and the CPU services the TIC
interrupt. The RETI at the end of the TIC ISR returns the core
to the instruction following the one that enabled power-down.
I
Power-down mode is terminated and the CPU services the
I
core to the instruction following the one that enabled power-
down. It should be noted that the I
interrupt enable bit (SERIPD) in the PCON SFR must first be
set to allow this mode of operation.
INT0 Interrupt
Power-down mode is terminated and the CPU services the
INT0 interrupt. The RETI at the end of the ISR returns the core
to the instruction following the one that enabled power-down.
The INT0 pin must not be driven low during or within two
machine cycles of the instruction that initiates power-down
mode. It should be noted that the INT0 power-down interrupt
enable bit (INT0PD) in the PCON SFR must first be set to allow
this mode of operation.
POWER-ON RESET
An internal power-on reset (POR) is implemented on the
ADuC832. For DV
the ADuC832 in reset. As DV
timer times out for approximately 128 ms before the part is
released from reset. The user must ensure that the power supply
has reached a stable 2.7 V minimum level by this time. Likewise
upon power-down, the internal POR holds the ADuC832 in reset
until the power supply drops below 1 V. Figure 92 illustrates the
operation of the internal POR in detail.
CORE RESET
2
2
DV
C or SPI Interrupt
C/SPI interrupt. The RETI at the end of the ISR returns the
INTERNAL
DD
2.45V TYP
1.0V TYP
Figure 92. Internal POR Operation
DD
128ms TYP
below 2.45 V, the internal POR holds
DD
rises above 2.45 V, an internal
2
C/SPI power-down
128ms TYP
1.0V TYP