X98014L128-3.3-Z Intersil, X98014L128-3.3-Z Datasheet - Page 10

• Manufacturer Part Number: X98014L128-3.3-Z
• Description: IC VIDEO DIGITIZER TRPL 128MQFP
• Manufacturer: Intersil
• Type: Video Digitizer, 3-Channel AFEr

Specifications of X98014L128-3.3-Z

• Applications: LCD TV/Monitor
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions
HSYNC
VSYNC
V
VREG
SYMBOL
V
VREG
COREADC
HS
V
VS
GND
GND
GND
BYPASS
V
CORE
NC
V
V
V
PLL
OUT
OUT
A
D
X
OUT
OUT
OUT
A
D
X
IN
3, 5, 8, 10, 15,
17, 21, 23, 27,
54, 67, 77, 89,
32, 43, 51, 53,
66, 76, 78, 88,
6, 11, 18, 20,
98, 108, 110,
99, 111, 124
52, 79, 109
120, 123
4, 9, 16
1, 2, 63
29, 35
30, 36
PIN
125
126
127
128
(Continued)
38
37
65
64
31
42
10
3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data.
This output is always purely horizontal sync (without any composite sync signals)
3.3V digital output.Artificial VSYNC output aligned with pixel data. VSYNC is generated 8 pixel clocks after
the trailing edge of HS
3.3V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is typically used to measure HSYNC
period. HS
and Macrovision signals if present on HSYNC
3.3V digital output. Buffered VSYNC output. For composite sync signals, this output will be asserted for the
duration of the disruption of the normal HSYNC pattern. This is typically used to detect the beginning of a
frame and measure the VSYNC period.
Power supply for the analog section. Connect to a 3.3V supply and bypass each pin to GND
Ground return for V
Power supply for all digital I/Os. Connect to a 3.3V supply and bypass each pin to GND
Ground return for V
Power supply for crystal oscillator. Connect to a 3.3V supply and bypass to GND
Ground return for V
Bypass these pins to GND
3.3V input voltage for V
Regulated output voltage for V
V
output can only supply power to V
Internal power for the ADC’s digital logic. Connect to VREG
with 0.1µF.
Internal power for the PLL’s digital logic. Connect to VREG
with 0.1µF.
Internal power for core logic. Connect to VREG
Reserved. Do not connect anything to these pins.
COREADC
OUT
and V
should be used to detect the beginning of a line. This output will pass composite sync signals
CORE
A
D
X
.
, V
and V
OUT
CORE
CORE
and bypass at input pins as instructed below. Do not connect to anything else - this
. This signal is usually not needed - use VSYNC
A
BYPASS
X98014
with 0.1µF. Do not connect these pins to each other or anything else.
, V
voltage regulator. Connect to a 3.3V source, and bypass to GND
PLL
COREADC
PLL
, V
.
COREADC
, V
COREADC
, and V
DESCRIPTION
IN
OUT
and V
or SOG
PLL
and V
and bypass each pin to GND
.
CORE
IN
CORE
OUT
OUT
.
; typically 1.9V. Connect only to V
through a 10Ω resistor and bypass to GND
through a 10Ω resistor and bypass to GND
.
OUT
as VSYNC source.
X
D
with 0.1µF.
with 0.1µF.
D
with 0.1µF.
A
PLL
D
with 0.1µF.
with 0.1µF.
March 8, 2006
,
FN8217.3
D
D