X98014L128-3.3-Z Intersil, X98014L128-3.3-Z Datasheet - Page 19

• Manufacturer Part Number: X98014L128-3.3-Z
• Description: IC VIDEO DIGITIZER TRPL 128MQFP
• Manufacturer: Intersil
• Type: Video Digitizer, 3-Channel AFEr

Specifications of X98014L128-3.3-Z

• Applications: LCD TV/Monitor
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 3 shows the corner frequency for different register
settings.
Register 0x0D[7:4] controls a programmable zero, allowing
high frequencies to be boosted, restoring some of the
harmonics lost due to excessive EMI filtering, cable losses, etc.
This control has a very large range, and can introduce high
frequency noise into the image, so it should be used judiciously,
or as an advanced user adjustment.
Table 4 shows the corner frequency of the zero for different
peaking register settings.
Offset DAC
The X98014 features a 10 bit Digital-to-Analog Converter
(DAC) to provide extremely fine control over the full channel
offset. The DAC is placed after the PGA to eliminate
(LSB = “x” = “don’t care”)
0X0D[7:4] VALUE
0x0D[3:0] VALUE
TABLE 4. PEAKING CORNER FREQUENCIES
000x
001x
010x
100x
101x
011x
110x
111x
0xA
0xB
0xC
0xD
0xE
0xF
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
TABLE 3. BANDWIDTH CONTROL
19
ZERO CORNER FREQUENCY
AFE BANDWIDTH
Peaking disabled
100MHz
130MHz
150MHz
180MHz
230MHz
320MHz
480MHz
780MHz
800MHz
400MHz
265MHz
200MHz
160MHz
135MHz
100MHz
115MHz
90MHz
80MHz
70MHz
65MHz
60MHz
55MHz
50MHz
X98014
interaction between the PGA (controlling “contrast”) and the
Offset DAC (controlling “brightness”).
In normal operation, the Offset DAC is controlled by the
ABLC™ circuit, ensuring that the offset is always reduced
to sub-LSB levels (See the following ABLC™ section for
more information). When ABLC™ is enabled, the Offset
registers (0x09, 0x0A, 0x0B) control a digital offset added
to or subtracted from the output of the ADC. This mode
provides the best image quality and eliminates the need for
any offset calibration.
If desired, ABLC™ can be disabled (0x17[0]=1) and the
Offset DAC programmed manually, with the 8 most
significant bits in registers 0x09, 0x0A, 0x0B, and the 2 least
significant bits in register 0x0C[7:2].
The default Offset DAC range is ±127 ADC LSBs. Setting
0x0C[0]=1 reduces the swing of the Offset DAC by 50%,
making 1 Offset DAC LSB the weight of 1/8th of an ADC
LSB. This provides the finest offset control and applies to
both ABLC™ and manual modes.
Automatic Black Level Compensation (ABLC™)
ABLC is a function that continuously removes all offset
errors from the incoming video signal by monitoring the
offset at the output of the ADC and servoing the 10 bit
analog DAC to force those errors to zero. When ABLC is
enabled, the user offset control is a digital adder, with 8 bit
resolution (See Table 5).
When the ABLC function is enabled (0x17[0]=0), the ABLC
function is executed every line after the trailing edge of
HSYNC. If register 0x05[5] = 0 (the default), the ABLC
function will not be triggered while the DPLL is coasting,
preventing any composite sync edges, equalization pulses,
or Macrovision signals from corrupting the black data and
potentially adding a small error in the ABLC accumulator.
After the trailing edge of HSYNC, the start of ABLC is delayed
by the number of pixels specified in registers 0x14 and 0x15.
After that delay, the number of pixels specified by register
0x17[3:2] are averaged together and added to the ABLC’s
accumulator. The accumulator stores the average black levels
for the number of lines specified by register 0x17[6:4], which
is then used to generate a 10 bit DAC value.
The default values provide excellent results with offset
stability and absolute accuracy better than 1 ADC LSB for
most input signals. Increasing the ABLC pixel width or the
ABLC bandwidth settings decreases the ABLC’s absolute
DC error further.
ADC
The X98014 features 3 fully differential, 140MSPS 8 bit
ADCs.
March 8, 2006
FN8217.3