X98014L128-3.3-Z Intersil, X98014L128-3.3-Z Datasheet - Page 17

• Manufacturer Part Number: X98014L128-3.3-Z
• Description: IC VIDEO DIGITIZER TRPL 128MQFP
• Manufacturer: Intersil
• Type: Video Digitizer, 3-Channel AFEr

Specifications of X98014L128-3.3-Z

• Applications: LCD TV/Monitor
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Input Coupling
Inputs can be either AC-coupled (default) or DC-coupled
(see register 0x05[1]). AC coupling is usually preferred since
it allows video signals with substantial DC offsets to be
accurately digitized. The X98014 provides a complete
internal DC-restore function, including the DC restore clamp
(See Figure 7) and programmable clamp timing (registers
0x14, 0x15, 0x16, and 0x23).
When AC-coupled, the DC restore clamp is applied every
line, a programmable number of pixels after the trailing edge
of HSYNC. If register 0x05[5] = 0 (the default), the clamp will
not be applied while the DPLL is coasting, preventing any
clamp voltage errors from composite sync edges,
equalization pulses, or Macrovision signals.
After the trailing edge of HSYNC, the DC restore clamp is
turned on after the number of pixels specified in the DC
Restore and ABLC™ Starting Pixel registers (0x14 and
0x15) has been reached. The clamp is applied for the
number of pixels specified by the DC Restore Clamp Width
Register (0x16). The clamp can be applied to the back porch
of the video, or to the front porch (by increasing the DC
Restore and ABLC™ Starting Pixel registers so all the active
video pixels are skipped).
R(GB)
R(GB)
R(GB)
R(GB)
GND
GND
IN
IN
1
1
2
2
Clamp DAC
DC Restore
VGA1
VGA2
V
V
IN
IN
V
+
–
CLAMP
17
DC Restoration
GENERATION
PGA
CLAMP
FIGURE 7. VIDEO FLOW (INCLUDING ABLC™)
Input
Bandwidth
Bandwidth
Control
ABLC
Block
To
X98014
If DC-coupled operation is desired, the input to the ADC will
be the difference between the input signal (R
example) and that channel’s ground reference (RGB
that example).
SOG
For component YUV signals, the sync signal is embedded
on the Y channel’s video, which is connected to the green
input, hence the name SOG (Sync on Green). The horizontal
sync information is encoded onto the video input by adding
the sync tip during the blanking interval. The sync tip level is
typically 0.3V below the video black level.
To minimize the loading on the green channel, the SOG
input for each of the green channels should be AC-coupled
to the X98014 through a series combination of a 10nF
capacitor and a 500Ω resistor. Inside the X98014, a window
comparator compares the SOG signal with an internal 4 bit
programmable threshold level reference ranging from 0mV
to 300mV below the minimum sync level. The SOG
threshold level, hysteresis, and low-pass filter is
programmed via register 0x04. If the Sync-On-Green
function is not needed, the SOG
unconnected.
Offset
ADC
10
Compensation (ABLC™) Loop
ABLC™
Offset
Fixed
8 bit ADC
Automatic Black Level
10
10
ABLC™
8
IN
Registers
Control
ABLC™
pin(s) may be left
Offset
8
8
Offset
Fixed
0x00
8
8
IN
1, for
To Output
Formatter
March 8, 2006
GND
FN8217.3
1 in