LMH1982SQE/NOPB National Semiconductor, LMH1982SQE/NOPB Datasheet - Page 12

IC CLK GEN MULTI RATE VID 32-LLP

LMH1982SQE/NOPB

Manufacturer Part Number
LMH1982SQE/NOPB
Description
IC CLK GEN MULTI RATE VID 32-LLP
Manufacturer
National Semiconductor
Type
Clock Generatorr
Datasheet

Specifications of LMH1982SQE/NOPB

Applications
Displays, Projectors, Receivers
Mounting Type
Surface Mount
Package / Case
32-LLP
For Use With
LMH1982SQEEVAL - BOARD EVAL FOR LMH1982SQE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
LMH1982SQETR
www.national.com
Supported Standards and Timing Formats
Table 1 lists the known supported standard timing formats and includes the relevant parameters that can be used to configure the
LMH1982 for the input reference and output timing. For the related programming instructions, see sections 4.0 INPUT REFER-
ENCE and 5.0 OUTPUT CLOCKS AND TOF.
Note 20: For some input reference formats, an alternative set of values for PLL 1 dividers and total lines per frame (REF_LPFM) is also shown in brackets
“[ ]”. This alternative set of values may be programmed if a lower PLL 1 phase comparison frequency is desired. The corresponding counter values for REF_LPFM
needs to be programmed for proper reference frame and output timing generation. See section 5.2.3 Reference Frame Timing.
Note 21: For any output HD format, an alternative set of counter values for total clocks per line (TOF_PPL) and total lines per frame (TOF_LPFM) is shown in
parenthesis “( )”. This alternative set of values can be programmed to generate any HD format TOF pulse using the 27 MHz SD_CLK instead of using the native
74.xx or 148.xx MHz HD_CLK. See section 5.2.2.1 HD Format TOF Generation using a 27 MHz TOF Clock.
1080p/59.94
1080p/29.97
1080p/23.98
NTSC, 525i
720p/59.94
720p/29.97
720p/23.98
PAL, 625i
1080p/60
1080p/50
1080p/30
1080p/25
1080p/24
720p/60
720p/50
720p/30
720p/25
720p/24
Format
525p
625p
Reference
Divider
PLL 1
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
1
1
1
1
1
5
1
1
5
1
1
2
1
5
1
1
5
1
1
1
1
INPUT TIMING PARAMETERS
Feedback
Divider
TABLE 1. Input Reference and Output Timing Parameters
[4290]
[4320]
[3000]
[3600]
[6000]
[7200]
[7500]
[2000]
[2400]
[4000]
[4800]
[5000]
[5005]
PLL 1
1716
1728
3003
1200
6006
1440
1500
3003
2002
4004
1000
1001
858
864
600
720
400
480
800
960
(Note 20)
PLL 1 Phase
Comparison
Frequency
8991.0090
8991.0090
15.7343
31.4685
[6.2937]
13.4865
26.9730
[5.3946]
15.625
4.4955
[11.25]
6.7433
28.125
[5.625]
(kHz)
31.25
[6.25]
18.75
[3.75]
[13.5]
56.25
33.75
[6.75]
45.0
[9.0]
37.5
[7.5]
22.5
[4.5]
18.0
[3.6]
67.5
27.0
[5.4]
Total Lines
per Frame
Counter
12
[105]
[125]
[150]
[150]
[150]
[150]
[150]
1125
[225]
1125
1125
[225]
1125
[225]
1125
1125
[225]
1125
[225]
1125
[225]
525
625
525
625
750
750
750
750
750
750
750
750
Frequency
74.176
74.176
74.176
148.35
74.176
74.176
Clock
(MHz)
(27.0)
(27.0)
(27.0)
(27.0)
(27.0)
(27.0)
(27.0)
(27.0)
(27.0)
(27.0)
(27.0)
(27.0)
(27.0)
(27.0)
(27.0)
74.25
74.25
74.25
74.25
74.25
148.5
148.5
74.25
74.25
74.25
27.0
27.0
27.0
27.0
(27)
OUTPUT TIMING PARAMETERS
Total Clocks
per Line
Counter
(3003)
(1200)
(6006)
(1440)
(1500)
(3003)
(2002)
(4004)
(1000)
(1001)
(600)
(720)
(400)
(480)
(800)
(960)
1716
1728
1650
1650
1980
3300
3300
3960
4125
4125
2200
2200
2640
2200
2200
2640
2750
2750
858
864
(Note 21)
Total Lines
per Frame
Counter
(1125)
(1125)
(1125)
(1125)
(1125)
(1125)
(750)
(150)
(750)
(150)
(150)
(750)
(750)
(375)
(225)
(225)
1125
1125
1125
1125
1125
1125
1125
1125
525
625
525
625
750
750
750
750
750
750
750
750
Frame
29.97
59.94
59.94
29.97
23.98
59.94
29.97
23.98
Rate
(Hz)
25
50
60
50
30
25
24
60
50
30
25
24

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