LMH1982SQE/NOPB National Semiconductor, LMH1982SQE/NOPB Datasheet - Page 20

• Manufacturer Part Number: LMH1982SQE/NOPB
• Description: IC CLK GEN MULTI RATE VID 32-LLP
• Manufacturer: National Semiconductor
• Type: Clock Generatorr

Specifications of LMH1982SQE/NOPB

• Applications: Displays, Projectors, Receivers
• Mounting Type: Surface Mount
• Package / Case: 32-LLP
• For Use With: LMH1982SQEEVAL - BOARD EVAL FOR LMH1982SQE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMH1982SQETR

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5.2.4 Input-Output Frame Rate Ratio
The input-output frame rate ratio is also used for resetting the
internal counters for output initialization. The ratio is the Input
Frame Rate / Output Frame Rate, in which the numerator and
denominator values are reduced to lowest integer factors.
The numerator value of this reduced ratio should be pro-
grammed to TOF_RST (register 09h-0Ah), and the denomi-
nator value is discarded.
Example:
If the input reference is 525i with a frame rate of 30/1.001 Hz
and the output format is 625i with a frame rate of 25 Hz, then:
Therefore, the numerator, 1200, should be programmed to
TOF_RST.
5.2.5 Output Frame Line Offset
The output clock and TOF pulse can be aligned to any line of
the reference frame by programming TOF_OFFSET (register
11h-12h) and subsequently programming the output initial-
ization sequence. The line offset value should be directly
programmed to TOF_OFFSET to delay or advance the out-
puts' alignment relative to the decoded reference frame timing
(see section 4.2 Reference Frame Decoder).
The TOF_OFFSET value must be greater than zero but less
than or equal to the programmed value for REF_LPFM (i.e.
0 < TOF_OFFSET
then program TOF_OFFSET equal to REF_LPFM instead of
zero (invalid value).
Example:
If an input reference with PAL timing comes from the
LMH1981, the H and V pulses will be aligned to within ΔT
which occurs on line 313 of the reference. In this case,
TOF_OFFSET can be set to 312d (138h) so the output frame
will align to Line 1 of the PAL reference (start of frame) after
the outputs are initialized. This example is illustrated in Figure
5.
Note: If the alternative set of divider and REF_LPFM values are pro-
REF_LPFM = Reference Format Total Lines per Frame
Frame rate ratio = (30/1.001) / 25 = 1200 / 1001
FIGURE 5. PAL Reference and Output TOF Pulse
grammed per (Note 20) for a lower PLL 1 phase comparison fre-
quency, then the output frame cannot be offset to any horizontal line
of the reference. Instead, the output frame can only be aligned to the
reference in 5 lines steps per 1 step of the TOF_OFFSET value, up
to a maximum of reference's total lines per frame divided by 5 (i.e.
REF_LPFM). This is because the phase comparison frequency
≤
(TOF_OFFSET = 312)
REF_LPFM). If no line offset is required,
30052434
HV
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5.3 Programming The Output Initialization Sequence
Before programming the output initialization (alignment) se-
quence, the following prerequisites must be met:
1.
2.
To ensure that the output clock and TOF pulse are properly
aligned and subsequently phase locked to the reference
frame, the output initialization sequence should be pro-
grammed accordingly.
During the output frame immediately prior to the frame the
initialization is to occur:
1.
2.
3.
5.3.1 TOF Output Delay Considerations
Due to the following conditions, the TOF pulse may be de-
layed or offset by more than one TOF clock period (t
1 pixel) even after output initialization:
1.
2.
3.
5.3.2 Output Clock Initialization without TOF
For applications that do not require the TOF pulse, it is still
necessary to program all output format registers prior to the
output initialization sequence. This is because the output ini-
tialization circuitry relies on the full and correct specification
of the output format. If the TOF output is not needed, it can
be put in Hi-Z mode by setting TOF_HIZ = 1 (register 08h).
5.4 Output Behavior Upon Loss Of Reference
After loss of reference (LOR), the LMH1982 will maintain the
TOF pulse without the input reference according to the ter-
minal counts of the reference clock; however, output frequen-
PLL 1 must be stable and locked to the input reference.
The desired output clock and TOF pulse timing must be
fully specified to the output format registers.
Set EN_TOF_RST = 1(register 0Ah) to enable output
alignment mode.
Toggle TOF_INIT (register 0Ah) from 0 to 1 to reset the
internal counters. On the next frame, the output clock and
TOF pulse will be initialized (aligned) to the reference
frame with line offset programmed to TOF_OFFSET.
Immediately after the initialization and before the next
output frame occurs, clear EN_TOF_RST and TOF_INIT
to 0. Otherwise, the output clock will be continually
aligned on every output frame while EN_TOF_RST = 1.
Continual alignment which may cause excessive jitter on
the output clock (from PLL 2, 3, or 4) due to slight
differences in the delay paths of the internal logic. This
occurrence of excessive clock jitter can be avoided by
disabling output alignment mode (EN_TOF_RST = 0)
immediately after the initialization sequence.
The delay paths of the internal logic used to generate and
align the TOF pulse is greater than one period of the TOF
clock. This can occur for HD format TOF pulses
generated using the 148 MHz native pixel clock. For HD
format TOF generation, it is recommended to use the 27
MHz SD clock as the TOF clock instead of the native HD
pixel clock as shown in section 5.2.2 Output Frame
Timing.
The H sync and/or V sync input pulses have excessive
jitter equal to or larger than half of a pixel period of the
selected output clock. Input sync jitter less than 3 ns
peak-to-peak is recommended.
PLL 1 is not completely phase locked or stable when the
output initialization is performed. The VCXO clock phase
error with respect to the H sync input should less than
one period of the selected TOF clock.
(H_FB signal in Figure 3) will be lower than the H sync input frequency
by 5x due to the use of the alternative divider values.
D_TOF
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