LMH1982SQE/NOPB National Semiconductor, LMH1982SQE/NOPB Datasheet - Page 28

• Manufacturer Part Number: LMH1982SQE/NOPB
• Description: IC CLK GEN MULTI RATE VID 32-LLP
• Manufacturer: National Semiconductor
• Type: Clock Generatorr

Specifications of LMH1982SQE/NOPB

• Applications: Displays, Projectors, Receivers
• Mounting Type: Surface Mount
• Package / Case: 32-LLP
• For Use With: LMH1982SQEEVAL - BOARD EVAL FOR LMH1982SQE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMH1982SQETR

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Bits 7-0: TOF Reset (TOF_RST)
This register contains the 8 LSBs of TOF_RST. When PLL 1
is phase locked to the reference, both H sync and V sync in-
puts are used to reset the frame-based counters used for
output TOF generation. The numerator value of the reduced
frame rate ratio should be programmed to TOF_RST. See
section 5.2.4 Input-Output Frame Rate Ratio.
Once TOF_RST is programmed, the outputs must be properly
initialized by either programming TOF_INIT or otherwise us-
ing an external TOF Init pulse (when PIN6_OVRD = 1).
Register 0Ah
Bits 4-0: TOF Reset (TOF_RST)
This register contains the 5 MSBs of TOF_RST. See the de-
scription for register 09h.
Bit 5: Output Initialization (TOF_INIT)
After enabling output alignment mode (EN_TOF_RST = 1),
the TOF_INIT bit should be programmed to reset the internal
counters and initialize (align) the outputs to the desired ref-
erence frame. The output initialization is triggered by pro-
gramming a positive bit transition (0 to 1) to TOF_INIT. See
section 5.3 Programming The Output Initialization Se-
quence.
Bit 6: TOF Pulse Output Polarity (POL_TOF)
This bit should be programmed to the desired TOF pulse po-
larity at the TOF output.
Bit 7: Output Alignment Mode (EN_TOF_RST)
This bit must be set (EN_TOF_RST = 1) to enable output
alignment mode prior to initialization per section 5.3 Program-
ming The Output Initialization Sequence. It is recommended
to clear this bit (EN_TOF_RST = 0) immediately after the out-
put initialization sequence has been programmed to prevent
excessive output jitter, as described in section 2.3 Output
Disturbance While Output Alignment Mode Enabled.
Register 0Bh
Bits 7-0: Total Pixels per Line for the Output Format
(TOF_PPL)
This register contains the 8 LSBs of TOF_PPL. TOF_PPL
should be programmed with total pixels per line for the desired
output format. TOF_PPL is used in specifying the output
frame rate. This should be specified prior to programming the
output initialization sequence. See section 5.2.2 Output
Frame Timing.
Register 0Ch
Bits 4-0: MSBs of Total Pixels per Line for the Output
Format (TOF_PPL)
This register contains the 5 MSBs of TOF_PPL. See the de-
scription for register 0Bh.
Bit 5: Output Clock Select for Output Top of Frame
(TOF_CLK)
This bit should be programmed to select the output TOF clock
reference according to the desired output format. The select-
ed TOF clock frequency is used in specifying the output frame
rate. Any output format, including HD, can use 27 MHz as the
TOF clock to generate its TOF pulse by programming the
output counter values corresponding to the 27 MHz SD clock
as shown in Table 1. See sections 5.2.1 Output TOF Clock
and 5.2.2 Output Frame Timing.
POL_TOF = 0: Negative polarity or active low signal.
POL_TOF = 1: Positive polarity or active high signal.
28
clock reference, where the SD frequency is set by SD_FREQ.
clock reference.
Bit 7-6: These non-programmable bits contain zeros.
Register 0Dh
Bits 7-0: LSBs of Total Lines per Frame for the Output
Format (TOF_LPFM)
This register contains the 8 LSBs of TOF_LPFM. TOF_LPFM
should be programmed with the total lines per frame for the
desired output format. TOF_LPFM is used in specifying the
output frame rate. This should be specified prior to program-
ming the output initialization sequence. See section 5.2.2
Output Frame Timing.
Register 0Eh
Bits 3-0: MSBs of Total Lines per Frame for the Output
Format (TOF_LPFM)
This register contains the 4 MSBs of TOF_LPFM. See the
description for register 0Dh.
Bit 7-5: These non-programmable bits contain zeros.
Register 0Fh
Bits 7-0: LSBs of Total Lines per Frame for the Input Ref-
erence Format (REF_LPFM)
This register contains the 8 LSBs of REF_LPFM. REF_LPFM
should be programmed with the total lines per frame for the
input reference format. REF_LPFM is used in specifying the
reference frame rate. This should be specified prior to pro-
gramming the output initialization sequence (section 5.2.3
Reference Frame Timing).
Register 10h
Bits 3-0: MSBs of Total Lines per Frame for the Input Ref-
erence Format (REF_LPFM)
This register contains the 4 MSBs of REF_LPFM. See the
description for register 0Fh.
Bit 7-4: These non-programmable bits contain zeros.
Register 11h
Bits 7-0: LSBs of Output Frame Offset (TOF_OFFSET)
This register contains the 8 LSBs of TOF_OFFSET.
TOF_OFFSET should be programmed with the desired line
offset to delay or advance the output timing relative to the
reference frame. This should be specified prior to program-
ming the output initialization sequence. See section 5.2.5
Output Frame Line Offset.
Register 12h
Bits 3-0: MSBs of Line Offset for the Output Top of Frame
(TOF_OFFSET)
This register contains the 4 MSBs of TOF_OFFSET. See the
description for register 11h.
Bit 7-4: These bits contain zeros (non-programmable)
9.8 PLL 1, 2, 3 Charge Pump Current Control Registers
Register 13h
Bits 4-0: PLL 1 Charge Pump Current Control (ICP1)
ICP1 can be programmed to specify the charge pump current
for PLL 1, which generates 27 MHz from the VCXO output.
The PLL 1 charge pump current, or I
gain parameters can be programmed to set and optimize PLL
TOF_CLK = 0: Selects the SD_CLK output as the output
TOF_CLK = 1: Selects the HD_CLK output as the output
CP1
, is one of the loop