LMH1982SQE/NOPB National Semiconductor, LMH1982SQE/NOPB Datasheet - Page 23

• Manufacturer Part Number: LMH1982SQE/NOPB
• Description: IC CLK GEN MULTI RATE VID 32-LLP
• Manufacturer: National Semiconductor
• Type: Clock Generatorr

Specifications of LMH1982SQE/NOPB

• Applications: Displays, Projectors, Receivers
• Mounting Type: Surface Mount
• Package / Case: 32-LLP
• For Use With: LMH1982SQEEVAL - BOARD EVAL FOR LMH1982SQE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMH1982SQETR

7.1.1 Loop Response Optimization Tips
The need to support various input reference formats will usu-
ally require a diverse range of PLL divider values, which can
each yield a different loop response assuming all other PLL
parameters are kept the same. Typically, it is desired to de-
sign and optimize the loop response across all supported
input formats without modification to the loop filter circuit. This
requires that the loop gain, K, be kept constant across all
supported divider values because K affects both BW and DF
equations. To keep a narrow range for K, the ratio (I
feedback divider) should be kept relatively constant. This can
be achieved by programming ICP1, so that I
FB_DIV for each supported input format.
It is suggested to start designing the loop filter component
values from the BW and DF equations with initial assumptions
of FB_DIV = 1716 (NTSC) and I
Once reasonable component values are achieved under
these initial assumptions, it is necessary to check that K can
be maintained over the expected range of FB_DIV by adjust-
ing I
practical minimum of 94 µA (ICP1 = 3d) to a maximum of 969
µA (ICP1 = 31d), which should provide adequate range to
maintain a narrow range for K assuming the suggested initial
values for FB_DIV and I
for K cannot be maintained within the usable range of I
then the loop filter design may need to be modified. Some
trial-and-error and iterative calculations may be necessary to
find an optimal loop filter.
In some loop filter designs, the calculated I
required for a target K value may be near or below the prac-
tical minimum of the I
also be possible to leverage the programmable reference and
feedback dividers by scaling up the values in proportion (i.e.
same reduced divider ratio). This would allow I
up by the same proportion to be within the usable I
range and maintain the same K value, since I
would be scaled by the same factor. For example, by scaling
the divider values by a factor of 5x, I
up by 5x such that its within the usable current range. This
technique of scaling FB_DIV and I
format has an alternative set of compatible divider values as
shown in Table 1.
7.1.2 Loop Filter Capacitors
It is suggested to use tantalum capacitors for C
stead of ceramic capacitors in the PLL loop filter, which is a
sensitive analog circuit. Ferroelectric ceramics, such as X7R,
X5R, Y5V, Y5U, etc., exhibit piezoelectric effects that gener-
ate electrical noise in response to mechanical vibration and
shock. This electrical noise can modulate the VCXO control
voltage and consequently induce clock jitter at high ampli-
tudes when the board and ceramic components are subjected
to vibration or shock. Tantalum capacitors can be used to
mitigate this effect.
7.2 Lock Time Considerations
The LMH1982 lock time or settling time is determined by the
loop response of PLL 1, which has a much lower loop band-
CP1
. The usable current range of I
CP1
CP1
current range. In this scenario, it may
were followed. If a narrow range
CP1
CP1
= 250 µA (default setting).
CP1
assumes that the input
can also be scaled
CP1
CP1
CP1
CP1
CP1
is limited to a
current that is
is scaled with
S
and FB_DIV
to be scaled
CP1
and C
current
CP1
P
CP1
in-
/
,
23
width compared to the integrated PLLs used to derive the
other output clock frequencies. Generally, the lock time is in-
versely proportional to the loop bandwidth; however, if the
loop response is not designed or programmed for sufficient
PLL stability, the lock time may not be predicted from the loop
bandwidth alone. Therefore, any parameter that affects the
loop response can also affect the overall lock time.
One way to reduce lock time is to widen the loop bandwidth
by programming a larger or maximum value for I
1 is locking; after PLL 1 is locked, I
vide a narrower loop bandwidth while maintaining a reason-
able damping factor.
7.3 VCXO Considerations
The recommended VCXO manufacturer part number is CTS
357LB3C027M0000, which has an absolute pull range (APR)
of ±50 ppm and operating temperature range of -20°C to +70°
C. A VCXO with a tighter APR can provide better output fre-
quency accuracy in Free Run operation; however, the APR
must be wider than the worst-case input frequency error in
order to achieve phase lock.
7.4 Free Run Output Jitter
The input voltage to VC_FREERUN (pin 1) should have suf-
ficient filtering to minimize noise over the frequency bands of
interest (i.e. SMPTE SDI jitter frequency bands) which can
cause VCXO input voltage modulation and thus free run out-
put clock jitter.
8.0 I
The protocol of the I
followed by a byte comprised of a seven-bit slave device ad-
dress and a read/write bit as the LSB. Therefore, the address
of the LMH1982 for write sequences is DCh (1101 1100) and
the address for read sequences is DDh (1101 1101). Figure
6, Figure 7, and Figure 8 show a write and read sequence
across the I
8.1 Write Sequence
The write sequence begins with a start condition, which con-
sists of the master pulling SDA low while SCL is held high.
The slave device address is sent next. The address byte is
made up of an address of seven bits (7:1) and the read/write
bit (0). Bit 0 is low to indicate a write operation. Each byte that
is sent is followed by an acknowledge (ACK) bit. When SCL
is high the master will release the SDA line. The slave must
pull SDA low to acknowledge. The address of the register to
be written to is sent next. Following the register address and
the ACK bit, the data byte for the register is sent. When more
than one data byte is sent, it is automatically incremented into
the next address location. See Figure 6. Note that each data
byte is followed by an ACK bit.
2
C INTERFACE PROTOCOL
2
C interface.
2
C interface begins with the start pulse
CP1
can be reduced to pro-
CP1
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while PLL