LMH1982SQE/NOPB National Semiconductor, LMH1982SQE/NOPB Datasheet - Page 16

• Manufacturer Part Number: LMH1982SQE/NOPB
• Description: IC CLK GEN MULTI RATE VID 32-LLP
• Manufacturer: National Semiconductor
• Type: Clock Generatorr

Specifications of LMH1982SQE/NOPB

• Applications: Displays, Projectors, Receivers
• Mounting Type: Surface Mount
• Package / Case: 32-LLP
• For Use With: LMH1982SQEEVAL - BOARD EVAL FOR LMH1982SQE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMH1982SQETR

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input can be used instead to select the reference port by ini-
tially setting I
The reference signals should be 3.3V LVCMOS signals within
the input voltage range specified in the Electrical Character-
istics table. The H sync and V sync input signals may have
analog timing, such as from the LMH1981 multi-format analog
video sync separator, or digital timing, such as from an FPGA
SDI deserializer.
4.1 Programming the PLL 1 Dividers
To genlock the outputs to the reference, it is necessary to
phase lock the VCXO clock (PLL 1) to the H sync input signal
by programming the PLL dividers. The PLL divider values for
each supported input reference format are given in Table 1.
The divider values can be determined by reducing the follow-
ing ratio to its lowest integer factors:
Where:
Table 3 shows the selection table with compatible PLL 1 ref-
erence divider values to program REF_DIV_SEL (register
03h). The PLL 1 feedback divider value can be directly pro-
grammed to FB_DIV (register 04h-05h).
Some supported input formats in Table 1 have two sets of
compatible divider values: reduced dividers and non-reduced
dividers. See Examples 2A and 2B below. Because the loop
response of PLL 1 is dependent on the feedback divider val-
ue, a lower loop bandwidth and phase comparison frequency
can be achieved by programming the non-reduced divider set
(see 7.0 LOOP RESPONSE ).
Examples:
1) For 1080i/59.94 input reference, the dividers are:
•
•
2A) For 1080i/50 input reference, the reduced dividers are:
•
•
2B) For 1080i/50 input reference, the non-reduced (alterna-
tive) dividers are:
•
•
4.2 Reference Frame Decoder
The LMH1982 features an internal frame decoder to deter-
mine the reference frame timing from only the H and V sync
input timing, which eliminates an extra input pin for an odd/
even field timing. The reference frame timing is required to
allow for output frame initialization (output TOF and clock
alignment) to the reference frame.
To allow for proper frame decoding and subsequent output
initialization, the H sync and V sync inputs must comply with
f
f
f
Feedback Divider = 1 to 8191 (0 is invalid)
Reference Divider = 1, 2 or 5
VCXO
VCXO
HSYNC
Reference divider = 5 (REF_DIV_SEL = 2h)
Feedback divider = 4004 (FB_DIV = FA4h)
Reference divider = 1 (REF_DIV_SEL = 1h)
Feedback divider = 960 (FB_DIV = 3C0h)
Reference divider = 5 (REF_DIV_SEL = 2h)
Feedback divider = 4800 (FB_DIV = 12C0h)
TABLE 3. PLL 1 Reference Divider Selection
REF_DIV_SEL
Register 03h
/ f
= 27 MHz VCXO frequency
= H sync input frequency
HSYNC
2
0h
1h
2h
C_RSEL = 0 (register 00h).
= Feedback Divider / Reference Divider
Reference Divider
2
1
5
16
the H-V sync timing offset specification, ΔT
formats, the H-V sync timing offset must be within ΔT
even fields and be outside ΔT
with this specification will ensure the internal frame counters
are reset only once per frame. For progressive formats, the
H-V timing offset must be within ΔT
Since the LMH1982 was designed for compatibility with the
LMH1981 sync separator, its H and V sync pulses will comply
with the ΔT
For digital timing from an FPGA SDI deserializer, the recov-
ered H and V sync pulses may be co-timed and be within
ΔT
frame counters to reset twice per frame and thus preclude
proper frame decoding and output initialization. As a simple
work-around, the designer may choose to configure the FP-
GA to gate the V sync signal, allowing only the even field
V pulses and gating off the odd field V pulses.
5.0 OUTPUT CLOCKS AND TOF
The LMH1982 has simultaneous LVDS output SD and HD
clocks and an output TOF pulse. For proper output format
timing generation and subsequent output initialization, it is
highly recommended to follow the programming sequence
below:
1.
2.
3.
5.1 Programming The Output Clock Frequencies
The SD clock frequency can be selected from Table 4 and
programmed to SD_FREQ (register 08h). PLL 1 and PLL 4
are used to generate the two SD clock rates but only one SD
clock can be selected at a time. If the SD_CLK output is not
needed, it can be put in Hi-Z mode by setting SD_HIZ = 1
(register 08h).
If 27 MHz is selected, the VCXO clock is directly converted
from a 3.3V single-ended clock at the VCXO input (pin 29) to
an LVDS clock at the SD_CLK output port (pins 23 and 24).
If 67.5 MHz is selected, the VCXO clock is used as an input
reference for PLL 4 to generate this SD clock frequency. In
some FPGA SD-SDI SerDes applications, the 67.5 MHz fre-
quency may be required as an SD reference clock instead of
the standard 27 MHz frequency.
The HD clock frequency can be selected from Table 5 and
programmed to HD_FREQ (register 08h). PLL 2 and PLL 3
are used to generate the four different HD clock rates but only
one HD clock can be selected at a time. If the HD_CLK output
is not needed, it can be put in Hi-Z mode by setting HD_HIZ
= 1 (register 08h).
Note: If 148.35 MHz is selected, it is required to follow the programming
SD_CLK (MHz)
HV
Program the output clock frequencies (section 5.1
Programming The Output Clock Frequencies).
Program the output format timing (section 5.2.2 Output
Frame Timing).
Program the output initialization sequence (section 5.3
Programming The Output Initialization Sequence).
sequence described in section 2.1 148.35 MHz PLL Initialization Se-
quence.
for both odd and even fields. This will cause the internal
67.5
TABLE 4. SD Clock Frequency Selection
27
HV
specification for any input reference format.
Register 08h
SD_FREQ
0
1
HV
for odd fields. Compliance
HV
for all frames.
HV
. For interlace
PLL#
1
4
HV
for