LMH1982SQE/NOPB National Semiconductor, LMH1982SQE/NOPB Datasheet - Page 14

• Manufacturer Part Number: LMH1982SQE/NOPB
• Description: IC CLK GEN MULTI RATE VID 32-LLP
• Manufacturer: National Semiconductor
• Type: Clock Generatorr

Specifications of LMH1982SQE/NOPB

• Applications: Displays, Projectors, Receivers
• Mounting Type: Surface Mount
• Package / Case: 32-LLP
• For Use With: LMH1982SQEEVAL - BOARD EVAL FOR LMH1982SQE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMH1982SQETR

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For I
section 9.0 I
TIONS.
2.1 148.35 MHz PLL Initialization Sequence
The following programming sequence is required to initialize
PLL 3 and generate a correct 148.35 MHz output once it is
selected as the HD_CLK; otherwise, the clock may have duty
cycle errors, frequency errors, and/or high jitter. This PLL ini-
tialization sequence must be programmed after switching
from another HD clock frequency or Hi-Z mode, as well as
after a device reset or power cycle condition. Each program-
ming step below represents a separate write sequence.
1.
2.
3.
After this sequence is completed, the 148.35 MHz clock will
operate correctly and normal device configuration can re-
sume. All other output clocks do not require this initialization
sequence for proper clock operation.
2.2 Enabling Genlock Mode
Upon device power up or reset, the default mode of operation
is Free Run mode. To enable Genlock mode, set GNLK = 1
(register 00h). Refer to section 3.2 Genlock Mode.
2.3 Output Disturbance While Output Alignment Mode
Enabled
When the output alignment mode is enabled (EN_TOF_RST
= 1) for a longer period than is required by the output initial-
ization sequence, the output signals can be abruptly phase-
aligned to the reference on every output frame. Continual
alignment can cause excessive phase “jumps” or jitter on the
output clock edge coinciding with the TOF pulse; this effect is
unavoidable and can be caused by slight differences in the
internal counter reset timing for the TOF generation and also
large input jitter. The characteristic of the output jitter can also
vary in severity from process variation, part variation, and the
selected clock reference frequency. This output jitter can only
be inhibited by setting EN_TOF_RST = 0 immediately follow-
ing the output initialization and before the subsequent output
frame.
2.4 Power Supply Sequencing
The V
lated by internal ESD structures that may become forward
biased when DV
dition, when prolonged and excessive, can trigger latch-up
and/or reduce the reliability of the device. Therefore, the
LMH1982 has a recommended power supply sequence.
On device power-up, the V
fore the DV
be brought down before the V
and ramp rates of the supplies should be considered to de-
termine the relative timing of the power-up and power-down
sequences such that DV
shown in the Absolute Maximum Ratings.
2
Program HD_FREQ = 11b and HD_HIZ = 0 (register 08h)
to select 148.35 MHz and enable the HD_CLK output.
Program a value of 1 to the following register parameters
(a single write sequence is valid for this step):
— FB_DIV = 1 (register 04h-05h)
— TOF_RST = 1 (register 09h-0Ah)
— REF_LPFM = 1 (register 0Fh-10h)
— EN_TOF_RST = 1 (register 0Ah)
Wait at least 2 cycles of the 27 MHz VCXO clock, then
program EN_TOF_RST = 0.
C interface control register map and definitions, refer to
DD
(3.3V) and DV
DD
2
C INTERFACE CONTROL REGISTER DEFINI-
supply. On power-down, the DV
DD
is higher than V
DD
DD
(2.5V) power supply pins are iso-
DD
does not exceed V
supply must be brought up be-
DD
supply. The starting points
DD
. Exposure to this con-
DD
DD
supply must
+0.3V as
14
To minimize the potential for latch-up, a Schottky diode can
be externally connected between the DV
and V
Schottky will ensure that V
V
Additionally, the device input pins (except for SDA and SCL
inputs) should not be driven prior to power-up due to the same
reasons provided above for the power pins. Otherwise, a
small series resistor should be used on each input pin to pro-
tect the device by limiting the current whenever the internal
ESD structures become forward biased.
Once both supplies are powered up in the proper sequence,
the device has a power on reset sequence that will reset all
registers to their default values.
2.5 Evaluating the LMH1982
For information about SDI jitter performance using the
LMH1982 with the LMH1981 sync separator, please refer to
the following application notes:
•
•
The LMH1982SQEEVAL Evaluation Board can be ordered
from National Semiconductor's website.
3.0 MODES OF OPERATION
The mode of operation describes the operation of PLL 1,
which can operate in either Free Run mode or Genlock mode
depending on the GNLK bit setting. If desired, the GEN-
LOCK input pin can be instead used to control the mode of
operation by initially setting I
3.1 Free Run Mode
The LMH1982 will enter Free Run mode when GNLK is set to
0. In Free Run mode, the VCXO will be free-running and in-
dependent of the input reference, and the output clocks will
maintain phase lock to the VCXO clock reference. Therefore,
the output clocks will have the same accuracy as the VCXO
clock reference.
The LMH1982 provides the designer with the option to define
the VCXO's free run control voltage by external biasing of the
VC_FREERUN input (pin 1). The analog bias voltage applied
to the VC_FREERUN input will be connected to the LPF out-
put (pin 31) though an internal switch (non-buffered, low
impedance), as shown in the Functional Block Diagram. The
resultant voltage at the LPF output will drive the control input
of the VCXO to set its free run output frequency. Thus, the
pull range of the VCXO imparts the same pull range on the
free run output clocks.
If VC_FREERUN is left floating, the VCXO control voltage will
be pulled to GND potential as the residual charge stored
across the loop filter will discharge through any existing leak-
age path.
3.2 Genlock Mode
The LMH1982 will enter Genlock mode when GNLK is set to
1. In Genlock mode, PLL 1 can be phase locked to the refer-
ence H sync input of the selected port; once the VCXO clock
reference is locked and stable, the output clocks and TOF
pulse can be aligned and phase locked to the reference. The
LMH1982 supports cross-locking, which allows the outputs to
be frame-locked to a reference format that is different from
the output format.
To genlock the outputs, the following programming sequence
is suggested:
DD
AN-1893: Demonstrating SMPTE-compliant SDI Output
Jitter using the LMH1982 and Virtex-5 GTP Transmitter
AN-1841: LMH1982 Evaluation Board User Guide
is brought up.
DD
supply (cathode). If DV
DD
is within about 0.3V of DV
2
C_GNLK = 0 (register 00h).
DD
is brought up first, the
DD
supply (anode)
DD
until