LMH1982SQE/NOPB National Semiconductor, LMH1982SQE/NOPB Datasheet - Page 21

• Manufacturer Part Number: LMH1982SQE/NOPB
• Description: IC CLK GEN MULTI RATE VID 32-LLP
• Manufacturer: National Semiconductor
• Type: Clock Generatorr

Specifications of LMH1982SQE/NOPB

• Applications: Displays, Projectors, Receivers
• Mounting Type: Surface Mount
• Package / Case: 32-LLP
• For Use With: LMH1982SQEEVAL - BOARD EVAL FOR LMH1982SQE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMH1982SQETR

cy accuracy will be determined by the VCXO, which may be
in Free Run or Holdover operation.
To disable output alignment to an arbitrary reference frame
when the reference is reapplied, set EN_TOF_RST = 0 before
the reference returns. After PLL 1 has re-locked to the refer-
ence, the outputs can be initialized to the desired reference
frame.
6.0 REFERENCE AND PLL LOCK STATUS
The LMH1982 features a reference detector and PLL lock
detector that can be used to indicate genlock status of the
input reference and device PLLs. Genlock status can be sam-
pled via the NO_REF and NO_LOCK status flag output pins
and the REF_VALID, SD_LOCK, and HD_LOCK status bits
(register 01h). Both the reference and PLL lock detectors may
be programmed for their respective detection thresholds ac-
cording to the needs of the application system. See Table 7
for a summary of the genlock status bits and status outputs
for different conditions.
The NO_REF and NO_LOCK outputs are derived from the
genlock status bits and given by the following two logic equa-
tions:
6.1 Reference Detection
In Genlock mode, a valid reference will be indicated by
NO_REF = 0 when all the criteria below are met. Otherwise,
a loss of reference (LOR) will be indicated by NO_REF = 1.
•
•
•
6.1.1 Programming the Loss of Reference (LOR)
Threshold
The reference detector's error threshold can be programmed
to H_ERROR (register 00h), which determines the maximum
number of missing H sync pulses before indicating an LOR.
The LOR threshold will be the H_ERROR value multiplied by
the PLL 1 reference divider value, as shown in Table 6.
If H_ERROR = 0, then the device will react after the first miss-
ing pulse. When the LOR threshold is exceeded, the NO_REF
REF_DIV_SEL
Register 03h
NO_REF = REF_VALID
NO_LOCK = (REF_VALID) (SD_LOCK) (HD_LOCK)
An H sync signal is applied to the input reference and
conforms to one of the standard formats in Table 1. A
V sync signal is not used in reference detection.
The PLL divide registers are programmed according to the
input reference format.
The control voltage of the VCXO is not within about 500
mV of the GND or V
0h
1h
2h
TABLE 6. LOR Threshold Selection
Reference
DD
Divider
supplies.
2
1
5
LOR Threshold
2 x H_ERROR
1 x H_ERROR
5 x H_ERROR
21
output will indicate LOR, and the device will default to either
Free Run or Holdover operation for as long as the reference
is lost. As the LOR threshold value is increased, the accuracy
for counting the actual number of missing H pulses may di-
minish due to frequency drifting by PLL 1.
Note: If the input reference is missing H pulses periodically, e.g. every ver-
6.2 PLL Lock Detection
In Genlock mode, PLL lock will be indicated by NO_LOCK =
0 when all the criteria below are met. Otherwise, a loss of lock
will be indicated by NO_LOCK = 1.
•
•
•
PLLs 2, 3, and 4 have high loop bandwidths, which allow them
to achieve lock quickly and concurrently while PLL 1 achieves
lock. Because PLL 1 has a much lower loop bandwidth, it will
dictate the overall lock indication time.
6.2.1 Programming the PLL Lock Threshold
PLL 1's lock detector threshold can be programmed to
LOCK_CTRL (register 01h), which determines the maximum
phase error between PLL 1's phase detector (PD) inputs be-
fore indicating an unlock or lock condition. The PD inputs are
the reference signal (H sync input / reference divider) and the
feedback signal (VCXO clock / feedback divider).
The lock detector will indicate loss of lock when the phase
error between the PD inputs is greater than the lock threshold
for three consecutive phase comparison periods. Conversely,
it will indicate valid lock when the phase error is less than the
lock threshold for three consecutive phase comparison peri-
ods.
A larger value for LOCK_CTRL will yield shorter lock indica-
tion time (although not actual lock time) at the expense of
higher output phase error when lock is initially indicated,
whereas a smaller value will yield the opposite effect.
6.2.2 PLL Lock Status Instability
It is possible for excessive jitter on the H input to indicate lock
instability through the NO_LOCK output, even if the VCXO
and output clocks are properly phase locked and no system-
level errors are occurring (e.g. bit errors). To reduce the
probability of false loss of lock indication or lock status insta-
bility, LOCK_CTRL can be increased to improve the lock
detector’s ability to tolerate a larger amount of input phase
jitter or phase error. This can help to ensure the NO_LOCK
output and SD_LOCK bit are stable when the reference signal
has large input jitter.
A valid reference is indicated (REF_VALID = 1).
PLL 1 or PLL 4 is phase locked to the input reference
(SD_LOCK = 1).
PLL 2 or PLL 3 is phase locked to the VCXO clock
reference (HD_LOCK = 1).
tical interval period, the PLL may not indicate a valid reference nor
achieve lock regardless of the H_ERROR value programmed. This is
because periodically missing pulses will translate to a lower average
frequency than expected. When the average input frequency falls
outside of the absolute pull range (APR) of the VCXO, the PLL will
not be able to frequency lock to the input reference.
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