LMH1982SQE/NOPB National Semiconductor, LMH1982SQE/NOPB Datasheet - Page 15

• Manufacturer Part Number: LMH1982SQE/NOPB
• Description: IC CLK GEN MULTI RATE VID 32-LLP
• Manufacturer: National Semiconductor
• Type: Clock Generatorr

Specifications of LMH1982SQE/NOPB

• Applications: Displays, Projectors, Receivers
• Mounting Type: Surface Mount
• Package / Case: 32-LLP
• For Use With: LMH1982SQEEVAL - BOARD EVAL FOR LMH1982SQE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMH1982SQETR

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Note: When Genlock mode is enabled, the LMH1982 will attempt to phase
3.2.1 Genlock Mode State Diagram
Figure 1 shows the Genlock mode state diagram for different
input reference and PLL lock conditions. It also includes Free
Run and Holdover states for the loss of reference operation,
specified by the HOLDOVER bit (register 00h). Each state
indicates the NO_REF and NO_LOCK status flag output con-
ditions.
3.2.2 Loss of Reference (LOR)
By configuring the HOLDOVER bit, the LMH1982 can default
to either Free Run or Holdover operation when a loss of ref-
erence (LOR) occurs in Genlock mode.
If HOLDOVER = 0 when a LOR occurs, the LMH1982 will
default to Free run operation (section 3.2.2.1 Free Run during
LOR) until a reference is reapplied.
Program the output clock frequency for the desired
output format. Refer to section 5.1 Programming The
Output Clock Frequencies.
Program the output TOF timing for the desired output
format. Refer to section 5.2 Programming The Output
Format Timing. It is required to complete this step for
proper output clock initialization (alignment) even if the
TOF pulse is not required.
Program the PLL 1 divider registers for the input
reference format. Refer to section 4.1 Programming the
PLL 1 Dividers.
Program GNLK = 1 to enable Genlock mode. See Note
below.
Program the output initialization to the desired reference
frame. Refer to section 5.3 Programming The Output
Initialization Sequence.
lock the PLLs to the input reference regardless of input timing stability.
Timing errors or instability on the inputs will cause the PLLs and out-
puts to also have instability. If output stability is a consideration during
periods of input uncertainty, it is suggested to gate off the input signals
from the LMH1982 until they are completely stable. Input signal gating
can be achieved externally using a discrete or FPGA logic buffer with
Hi-Z (tri-state) output and a pull-up or pull-down resistor, depending
on the input pulse signal polarity.
FIGURE 1. Genlock Mode State Diagram
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If HOLDOVER = 1 when a LOR occurs, the LMH1982 will
default to Holdover operation (section 3.2.2.2 Holdover during
LOR) until a reference is reapplied.
When the input reference is reapplied, the LMH1982 will im-
mediately attempt to phase lock the output clocks to the
reference.
3.2.2.1 Free Run during LOR
Free Run mode (GNLK = 0) differs from Free Run operation
due to LOR in Genlock mode (GNLK = 1) in the following way:
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•
3.2.2.2 Holdover during LOR
In Holdover operation, the LPF output is put into high
impedance mode, which allows the loop filter to temporarily
hold the residual charge stored across it (i.e. the control volt-
age) immediately after LOR is indicated by the NO_REF
status flag. Holdover operation can help to temporarily sustain
the output clock accuracy upon LOR. The duration that the
residual control voltage level can be sustained within a toler-
able level depends primarily on the charge leakage on the
loop filter. A typical VCXO has an input impedance of several
tens of kΩ, which will be the dominant leakage path seen by
the loop filter. As the leakage current discharges the residual
control voltage to GND, the output frequencies of the VCXO
and LMH1982 will drift accordingly. If a longer time constant
is required, a precision op amp with low input bias current and
rail-to-rail input and output (e.g. LMP7701) can be used to
buffer the control voltage. The buffer will isolate the relatively
low input impedance of the VCXO and reduce the charge
leakage on the loop filter during Holdover.
The output frequency accuracy will degrade as the VCXO ac-
curacy drifts with the decaying control voltage. Moreover,
because the H_ERROR setting (register 00h) affects the ref-
erence error threshold for LOR indication, a higher setting for
H_ERROR may result in reduced output accuracy upon LOR
indication compared to when H_ERROR = 0. For more infor-
mation on programming H_ERROR, see section 6.1.1 Pro-
gramming the Loss of Reference (LOR) Threshold.
4.0 INPUT REFERENCE
The LMH1982 features two reference ports (A and B) with H
sync and V sync inputs which are used for phase locking the
outputs in Genlock mode. The reference port can be selected
by programming RSEL (register 00h). If desired, REF_SEL
FIGURE 2. Loop Filter with Optional Op Amp to Isolate
In Free Run mode, the outputs will free run regardless of
the presence or loss of reference.
In Genlock mode, the outputs will free run only during
LOR; once a reference is present, free run operation will
cease as the PLLs will immediately attempt to phase lock
the output clocks to the reference.
VCXO's Low Input Impedance
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