LMH1982SQE/NOPB National Semiconductor, LMH1982SQE/NOPB Datasheet - Page 4

• Manufacturer Part Number: LMH1982SQE/NOPB
• Description: IC CLK GEN MULTI RATE VID 32-LLP
• Manufacturer: National Semiconductor
• Type: Clock Generatorr

Specifications of LMH1982SQE/NOPB

• Applications: Displays, Projectors, Receivers
• Mounting Type: Surface Mount
• Package / Case: 32-LLP
• For Use With: LMH1982SQEEVAL - BOARD EVAL FOR LMH1982SQE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMH1982SQETR

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Pin Descriptions
Notes
1. Refer to section 2.4 Power Supply Sequencing.
2. To control reference selection via the REF_SEL pin instead of the I
3. To override reference control via pin 6 and instead use pin 6 as an logic input for output initialization, program PIN6_OVRD = 1 (register 02h); accordingly, the
TOF_INIT bit (register 0Ah) will be ignored and reference selection must be controlled via I
4. Must be
5. SDA and SCL pins each require a 4.7 kΩ (typ) pull-up resistor to the V
6. To control mode selection via the GENLOCK pin instead of the I
2, 10, 18, 22, 26, 30
3, 21, 27, 28, 32
Pin No.
≤
19, 20
23, 24
V
11
12
13
14
15
16
17
25
29
31
–
1
4
5
6
7
8
9
DD
+0.3V. Refer to section 2.4 Power Supply Sequencing.
HD_CLK, HD_CLK
SD_CLK, SD_CLK
VC_FREERUN
I
2
GENLOCK
NO_LOCK
Pin Name
C_ENABLE
REF_SEL
NO_REF
HREF_A
HREF_B
VREF_A
VREF_B
RESET
VCXO
DV
GND
DAP
SDA
TOF
SCL
LPF
V
DD
DD
2
C interface (default), program I
2
C interface (default), program I
I/O
I/O
O
O
O
O
O
O
–
–
–
–
I
I
I
I
I
I
I
I
I
I
I
DD
supply.
4
Signal Level
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
2
Supply
Analog
Supply
Supply
Supply
Analog
C.
LVDS
LVDS
I
I
2
2
C
C
2
C_GNLK = 0 (register 00h).
2
C_RSEL = 0 (register 00h).
Die Attach Pad (Connect to GND)
Free Run Control Voltage Input
Ground
3.3V Supply
H sync Input, Reference A
V sync Input, Reference A
Reference Select
H sync Input, Reference B
V sync Input, Reference B
2.5V Supply
I
I
I
Mode Select
Device Reset
Reference Status Flag
Lock Status Flag
HD Clock Output
SD Clock Output
Top of Frame Pulse
VCXO Clock Input
VCXO PLL Loop Filter
2
2
2
C Data
C Clock
C Enable
5
5
Pin Description
1
4
6
2, 3