KSZ8841-16 Micrel Semiconductor, KSZ8841-16 Datasheet
KSZ8841-16
Available stocks
Related parts for KSZ8841-16
KSZ8841-16 Summary of contents
Page 1
... Figure 1. KSZ8841M Functional Diagram 1 KSZ8841-16/32 MQL/MVL/MVLI with Non-PCI Interface Data Sheet Rev 1 ...
Page 2
... RX/TX FIFO buffers • Early TX/RX functions to minimize latency through the device • Optional to use external serial EEPROM configuration for both KSZ8841-16MQL and KSZ8841-32MQL • Single 25MHz reference clock for both PHY and MAC Network Features • Fully integrated to comply with IEEE802.3u standards • ...
Page 3
... KSZ8841-16MVL KSZ8841-32MVL KSZ8841-16MVLI –40 KSZ8841-16MQL-Eval Evaluation Board for the KSZ8841-16MQL Contacts Location Address Corporate HQ 2180 Fortune Drive Eastern USA 93 Branch Street Central USA 2425 N.Central Expressway, Suite 351 Western USA 2180 Fortune Drive China Room 712, Block B, Intl. Chamber of Commerce Bldg ...
Page 4
... Markets ................................................................................................................................................................2 Ordering Information..........................................................................................................................................3 Contacts ..............................................................................................................................................................3 Revision History .................................................................................................................................................3 Contents ..............................................................................................................................................................4 List of Figures .....................................................................................................................................................7 List of Tables.......................................................................................................................................................8 Pin Configuration for KSZ8841-16 Chip (8/16-Bit) ...........................................................................................9 Pin Description for KSZ8841-16 Chip (8/16-Bit).............................................................................................10 Pin Configuration for KSZ8841-32 Chip (32-Bit) ............................................................................................15 Pin Description for KSZ8841-32 Chip (32-Bit)................................................................................................16 Functional Description.....................................................................................................................................21 Functional Overview.........................................................................................................................................21 Power Management.................................................................................................................................................... 21 Power down ...
Page 5
... Bank 7 Wakeup Frame 3 CRC1 Register (0x02): WF3CRC1 ......................................................................................................... 56 Bank 7 Wakeup Frame 3 Byte Mask 0 Register (0x04): WF3BM0 ................................................................................................. 56 Bank 7 Wakeup Frame 3 Byte Mask 1 Register (0x06): WF3BM1 ................................................................................................. 57 Bank 7 Wakeup Frame 3 Byte Mask 2 Register (0x08): WF3BM2 ................................................................................................. 57 Bank 7 Wakeup Frame 3 Byte Mask 3 Register (0x0A): WF3BM3 ................................................................................................. 57 Bank 8 – 15: Reserved ................................................................................................................................................................... 57 November 2005 5 KSZ8841-16/32 MQL/MVL Rev 1.3 ...
Page 6
... Bank 49 Port 1 Status Register (0x04): P1SR ................................................................................................................................ 76 Banks 50 – 63: Reserved................................................................................................................................................................ 77 MIB (Management Information Base) Counters.............................................................................................78 Additional MIB Information .............................................................................................................................................................. 79 (1) Absolute Maximum Ratings (1) Operating Ratings ..........................................................................................................................................80 (1) Electrical Characteristics ..............................................................................................................................81 Timing Specifications.......................................................................................................................................82 Asynchronous Timing without using Address Strobe (ADSN = 0)................................................................................................... 82 November 2005 ..........................................................................................................................80 6 KSZ8841-16/32 MQL/MVL Rev 1.3 ...
Page 7
... List of Figures Figure 1. KSZ8841M Functional Diagram ..................................................................................................................................................1 Figure 2. Standard – KSZ8841-16 MQL 128-Pin PQFP (Top View)........................................................................................................... 9 Figure 3. Option – KSZ8841-16 MVL 128-Pin PQFP (Top View) ............................................................................................................... 9 Figure 4. Standard – KSZ8841-32 MQL 128-Pin PQFP (Top View)......................................................................................................... 15 Figure 5. Option – KSZ8841-32 MVL 128-Pin PQFP (Top View) ............................................................................................................. 15 Figure 6 ...
Page 8
... Table 22. Synchronous Write (VLBUSN = 0) Timing Parameters ............................................................................................................ 88 Table 23. Synchronous Read (VLBUSN = 0) Timing Parameters ............................................................................................................ 89 Table 24. Auto Negotiation Timing Parameters........................................................................................................................................ 90 Table 25. Reset Timing Parameters ......................................................................................................................................................... 91 Table 26. EEPROM Timing Parameters................................................................................................................................................... 92 Table 27. Transformer Selection Criteria.................................................................................................................................................. 93 Table 28. Qualified Single Port Magnetics................................................................................................................................................ 93 Table 29. Typical Reference Crystal Characteristics ................................................................................................................................ 93 November 2005 8 KSZ8841-16/32 MQL/MVL Rev 1.3 ...
Page 9
... Figure 2. Standard – KSZ8841-16 MQL 128-Pin PQFP (Top View) DGND VDDIO DGND DGND VDDIO Figure 3. Option – KSZ8841-16 MVL 128-Pin PQFP (Top View) November 2005 ...
Page 10
... Micrel Confidential Pin Description for KSZ8841-16 Chip (8/16-Bit) Pin Pin Name Type Number 1 TEST_EN I 2 SCAN_EN I 3 P1LED2 Opu 4 P1LED1 Opu 5 P1LED0 Opu 6 NC Opu 7 NC Opu 8 NC Opu 9 DGND Gnd 10 VDDIO P 11 RDYRTNN Ipd 12 BCLK Ipd 13 NC Ipu 14 PMEN Opu ...
Page 11
... Port 1 LED indicator See the description in pins 3, 4, and 5. EEPROM Data Out This pin is connected to DI input of the serial EEPROM. EEPROM Serial Clock µ serial output clock to load configuration data from the serial EEPROM. EEPROM Data In 11 KSZ8841-16/32 MQL/MVL Rev 1.3 ...
Page 12
... DD No Connect No Connect Analog ground No Connect No Connect 1.2 analog V input power supply from VDDCO (pin24) through external Ferrite DD bead and capacitor. Analog ground No connect No connect Set physical transmits output current. Pull-down this pin with a 3.01K 1% resistor to ground. Analog ground 12 KSZ8841-16/32 MQL/MVL Rev 1.3 ...
Page 13
... BE1N for 8-bit bus mode). No Connect Digital core ground 1.2V digital core V input power supply from VDDCO (pin24) through external DD Ferrite bead and capacitor. 3.3V digital V input power supply for IO with well decoupling capacitors. DDIO No Connect No Connect No Connect No Connect No Connect No Connect No Connect 13 KSZ8841-16/32 MQL/MVL Rev 1.3 ...
Page 14
... IO with well decoupling capacitors. DDIO No Connect Data 15 Data 14 Data 13 Data 12 Data 11 Data 10 Data 9 Data 8 Data 7 Data 6 Data 5 Data 4 Data 3 Digital IO ground Digital core ground 3.3V digital V input power supply for IO with well decoupling capacitors. DDIO Data 2 Data 1 Data 0 14 KSZ8841-16/32 MQL/MVL Rev 1.3 ...
Page 15
... D9 D8 117 D7 118 (Top View) D6 119 D5 120 D4 121 D3 122 123 124 125 D2 126 D1 127 D0 128 15 KSZ8841-16/32 MQL/MVL ISE ...
Page 16
... This pin should be tied Low or unconnected asynchronous mode. DATA Chip Select Not (For KSZ8841-32 Mode only) Chip select signal for QMU data register (QDRH, QDRL), active Low. When DATACSN is Low, the data path can be accessed regardless of the value of 16 KSZ8841-16/32 MQL/MVL [0,1] — 100Link/Act 10Link/Act ...
Page 17
... EEPROM is disabled when this pin is pull-down or no connect. Port 1 LED indicator See the description in pins 3, 4, and 5. EEPROM Data Out 17 KSZ8841-16/32 MQL/MVL tected by KSZ8841M. oth EISA-like and VLBus-like ce only), the KSZ8841M drives this pin low to indica te an interrupt status bit is set, this pin need ...
Page 18
... DD No Connect No Connect Analog ground No Connect No Connect 1.2 analog V input power supply from VDDCO (pin24) through external Ferrite DD bead and capacitor. Analog ground No connect 18 KSZ8841-16/32 MQL/MVL the rising edge of ADSN indicates the Power down; High = Normal operation). rough external Ferrite Rev 1.3 d ...
Page 19
... Byte Enable 0 Not, Active low for Data byte 0 enable Data 31 Digital core g round 1.2V digital core V input power supply from VDDCO (pin24) through external DD Ferrite bead and capacitor. 3.3V digital V input power supply for IO with well decoupling capacitors. DDIO Data 30 Data 29 Data 28 Data 27 19 KSZ8841-16/32 MQL/MVL Rev 1.3 ...
Page 20
... IO with well decoupling capacitors. DDIO Data 16 Data 15 Data 14 Data 13 Data 12 Data 11 Data 10 Data 9 Data 8 Data 7 Data 6 Data 5 Data 4 Data 3 nd Digital IO g round nd Digital core ground 3.3V digital V input power supply for IO with well decoupling capacitors. DDIO Data 2 Data 1 Data 0 d utput. 20 KSZ8841-16/32 MQL/MVL Rev 1.3 ...
Page 21
... Bank 6 and is enabled by bit 2 in wakeup frame control register. 21 KSZ8841-16/32 MQL/MVL that wake frames can be detected. Conversely, a Rev 1.3 ...
Page 22
... Magic Packet (MP) frame agic Packet frame. For instance, the sequence could TCP/IP packet or an network without affecting its ability to wake-up a node at the d transmission. 22 KSZ8841-16/32 MQL/MVL he LAN Rev 1.3 ...
Page 23
... A differential input receiver circuit and parated into clock signal and NRZ data. A squelch circuit rejects signals with n similar devices, the KSZ8841M supports HP-Auto MDI/MDI-X and 23 KSZ8841-16/32 MQL/MVL ristics, and then tunes itself for optimization restoration circuit is used to Rev 1.3 ...
Page 24
... Cable Transmit Pair Modular Connector (RJ-45) HUB (Repeater or Switch) Figure 7. Typical Cros sover Cable Connection 24 KSZ8841-16/32 MQL/MVL MDI-X Signals 1 RD+ 2 RD- 3 TD ...
Page 25
... Attempt Auto Listen for 100BASE-TX Negotiation Idles Join Flow Link Mode Set ? Link Mode Set Figure 8. Auto Negotiation and Parallel Operation 25 KSZ8841-16/32 MQL/MVL d 02.3 committee to allow the port to to select th e bes t common mode of operation. In auto ach othe uto negotiation is not supported or the ...
Page 26
... The KSZ8841M implements the IEEE standard 802.3 binary exponential back-off algorithm in half-duplex mode. After 16 collisions, the packet is dropped. L ate Collision If a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped. November 2005 edance mismatches. er-optic operation is not supported. 26 KSZ8841-16/32 MQL/MVL Rev 1.3 ...
Page 27
... KSZ8841-16/32 MQL/MVL e deferred state. If the port has packets to mbedded processors. The use of glue Rev 1.3 ...
Page 28
... For example, For a 32-bit system/host data bus, the KSZ8841M allows an 8-bit, 16-bit, and 32-bit data transfer (KSZ8841-32MQL). For a 16-bit system/host data bus, the KSZ8841M allows an 8-bit and 16-bit data transfer (KSZ8841-16MQL). For an 8-bit system/host data bus, the KSZ8841M only a The KSZ8841M does not support internal data byte-swap but it does support internal data word-swap. This means that the system/host data bus HD[7:0] must connect to both D[7:0] and D[15:8] for an 8-bit data bus interface ...
Page 29
... YRTNN are de-asserted and stay at the same logic level r. host) are local device decoding and having stable address thro pplication is ISA-like bus interface using latched address signals as 29 KSZ8841-16/32 MQL/MVL write (High) or read (Low) transfer. ) not by ouping tch is required, use the rising edge of binatorial decode of AEN and A[15:4]. ...
Page 30
... Figure 19. terface (VLBUSN = 1): l inverter is enabled and connected between BE0N and BE1N even 30 KSZ8841-16/32 MQL/MVL RN to latch write data. nded target. The data transfer is the same as the r on the system board us-like and the other for EISA-like (DMA type C) until RDYRTNN is asserted. The assert the RDYRTNN signal ...
Page 31
... Glue Logic (VLBUSN = 1) Glue Logic Address Latch Note: To use DATACSN & 32-bit only for Central decode KSZ8841-16 HA[ HA[15:2] A [15:2] HD[7:0] D[7:0] HD[15:8] D[15:8] HA[0] BE0N BE1N nSBHE 16-bit Data Bus (for example: ISA-like) 31 KSZ8841-16/32 MQL/MVL KSZ8841M BIU Local decode Asynchronous Interface Synchronous Interface Local decode (VLBUSN = 0) KSZ8841-32 GND A[1] HA[15:2] A[15:2] D[7:0] HD[7:0] HD[15:8] D[15:8] D[23:16] HD[23:16] D[31:24] ...
Page 32
... November 2005 Bit Byte Control Word Byte Count Transmit Packet Data (maximum size is 1916) Table 3. Frame Format for Transmit Queue tion Table 4. Transmit Control Word Bit Fields 32 KSZ8841-16/32 MQL/MVL pending on whether Bit Byte Rev 1.3 ...
Page 33
... Address Offset nd 2 Byte 0 Status Word 2 Byte Count Receive Packet Data (maximum size is 1916) Table 6. Fra me Format for Receiv rame ndicates that this frame has a multicast address (including the broadcast nicast address. 33 KSZ8841-16/32 MQL/MVL Bit Byte e Queue le 5. Rev 1.3 ...
Page 34
... Host MAC Address Byte 6 Reserved Reserved ConfigParam (see Table 10) Not used for KSZ8841M (available for user to use) Table 9. KSZ8841M EEPROM Format 34 KSZ8841-16/32 MQL/MVL tion and does not cause any frame n or had a premature M devices). The EEPROM 7 0 Host MAC Address Byte 1 ...
Page 35
... Async 8-bit bus select 1= bus is configured for 16-bit w idth 0= bus is configured for 8-bit wi dth This bit is loaded to bit 0 of PMC R register (32-bit width, KSZ8841-3 2MQL , don’t care this bit setting) Table 10. ConfigParam Word in EEPROM Format 35 KSZ8841-16/32 MQL/MVL upon s D3_hot Rev 1.3 ...
Page 36
... The ports 1 near-end loopback path is illustrated in the fo PHY Port 1 Near-end (remote) Loopback PMD1/PMA1 PCS1 MAC1 RXQ/TXQ QMU/DMA Bus I/F Unit Figure 11. PHY Port 1 Near-end (Remote) Loopback Path 36 KSZ8841-16/32 MQL/MVL at the PHY port’s Y port’s transmit of register P1SCSLMD llowing Figure TXP1 / TXM1 Rev 1.3 ...
Page 37
... The following I/O Space Mapping Tables apply 32-bit bus products. Depending on the bus interface used and byte enable signals (BE[3:0]N control byte access), each I/O access can be performed as an 8-bit, 16-bit, or 32-bit o peration. (The KSZ8841M is not limited to 8/16-bit performance and 32-bit read/write are also supported). November 2005 information, and transferring packets by reading 37 KSZ8841-16/32 MQL/MVL Rev 1.3 ...
Page 38
... Management Capabilities [7:0] Reserved Reserved Power Management Capabilities [15:8] Wakeup Frame Control [7:0] Reserved Wakeup Frame Control [15:8] Reserved Bank Select [7:0] Bank Select [15:8] 38 KSZ8841-16/32 MQL/MVL Bank 4 Bank 5 Bank 6 Wakeup Wakeup Wakeup Frame0 Frame1 Frame2 CRC0 [7:0] CRC0 [7:0] CRC0 [7:0] Wakeup Wakeup Wakeup Frame0 Frame1 Frame2 CRC0 [15:8] CRC0 [15:8] ...
Page 39
... To 0xF 0xE 0xE - 0xF 0xF November 2005 Bank Location Bank 9 Bank 10 Bank 11 Reserved R es Reserved Res Reserved Reserved Reserved Bank Select [7:0] Bank Select [15:8] 39 KSZ8841-16/32 MQL/MVL Bank 12 Bank 13 Bank 14 erved erved Bank 15 Rev 1.3 ...
Page 40
... Management Low Transmit Control/Status [7:0] [7:0] [7:0] QMU Data Early Power Low Transmit Managem ent Control/Status [15:8] [15:8] [15:8] QMU Data Early High Receive [7:0] [7:0] QMU Data Early High Receive [15:8] [15:8] Bank Select [7:0] Bank Select [15:8] 40 KSZ8841-16/32 MQL/MVL Bank 20 Bank 21 Bank 22 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bank 23 Rev 1.3 ...
Page 41
... To 0xF 0xE 0xE - 0xF 0xF November 2005 Bank Location Bank 25 Bank 26 Bank 27 Reserved Reserved Reserved Reserved Res Reserved Reserved Bank Select [7:0] Bank Select [15:8] 41 KSZ8841-16/32 MQL/MVL Bank 28 Bank 29 Bank 30 erved Bank 31 Rev 1.3 ...
Page 42
... Chip Global Control 0xB [15:8] 0xC 0xC - 0xD 0xD 0xC To 0xF 0xE 0xE - 0xF 0xF November 2005 Bank Location Bank 33 Bank 34 Bank 35 Reserved Reserved Reserved Reserved Reserved Bank Select [7:0] Bank Select [15:8] 42 KSZ8841-16/32 MQL/MVL Bank 36 Bank 37 Bank 38 Res erved Res erved Bank 39 Rev 1.3 ...
Page 43
... Indirect Access Data 4 [7:0] Reserved Indirect Access Data 4 [15:8] Indirect Access Data 5 [7:0] Reserved Indirect Access Data 5 [15:8] Reserved Bank Select [7:0] Bank Select [15:8] 43 KSZ8841-16/32 MQL/MVL Bank 44 Bank 45 Bank 46 PHY1 MII- Register Basic Control [7:0] Reserved PHY1 MII- Register Basic Control [15:8] PHY1 MII- Register Basic Status [7:0] Reserved ...
Page 44
... Bank Location Bank 49 Bank 50 Bank 51 Port 1 PHY Special Control/Status, LinkM D [7:0] Port 1 PHY Special Control/Status, LinkMD [15:8] Port 1 Control 4 [7:0] Port 1 Control 4 [15:8] Port 1 Status [7:0] Port 1 Status [15:8] Bank Select [7:0] Bank Select [15:8] 44 KSZ8841-16/32 MQL/MVL Bank 52 Bank 53 Bank 54 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bank 55 Rev 1.3 ...
Page 45
... To 0xB 0xA 0xA - 0xB 0xB 0xC 0xC - 0xD 0xD 0xC To 0xF 0xE 0xE - 0xF 0xF November 2005 Bank Location Bank 57 Bank 58 Bank 59 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bank Select [7:0] Bank Select [15:8] 45 KSZ8841-16/32 MQL/MVL Bank 60 Bank 61 Bank 62 Bank 63 Rev 1.3 ...
Page 46
... These bits are compared against the address on the bus ADDR[15:8] to determine the BASE for the KSZ8841M registers. BARL Base Address Low These bits are compared against the address on the bus ADDR[7:5] to determine the BASE for the KSZ8841M register s. Reserved. 46 KSZ8841-16/32 MQL/MVL e bits , the use rea d b ack thes e Rev 1 ...
Page 47
... Write 1 to clear. Reserved. r (0x08): BBLR Description Reserved. BRL Burst Length (for burst read and write) 000: single. 011: fixed bur st read length of 4. 101: fixed burst read length of 8. 111: fixed burst read length of 16. Reserved. 47 KSZ8841-16/32 MQL/MVL occur simultaneously. Rev 1.3 ...
Page 48
... Middle The middle word of the MAC address. ter bit fields for high word MAC address. Description MARH MAC Address High The Most significant word of the MAC address. 48 KSZ8841-16/32 MQL/MVL word location 0x1 of the 01:23:45:67:89:AB, where the bytes are C address. Rev 1.3 ...
Page 49
... Bit 1: Serial Clock. This bit di rectly controls the device’s EESK pin. Bit 0: Chip Select for EEPROM. This bit directly controls the device’s EECS pin. 49 KSZ8841-16/32 MQL/MVL therwise, tie it to Low external are if the EEPROM Software Access bit is . Rev 1.3 ...
Page 50
... KSZ8841M power state. The value of this bit is loaded from the PME_D2 bit of 0x6 in the serial EEPROM (without an EEPROM, this bit defaults to 0). 50 KSZ8841-16/32 MQL/MVL est has failed. lf Test has failed. ffected by a software reset. power management capabilities. These bits ...
Page 51
... D1_SUP bit of 0x6 in the serial EEPROM (without an EEPROM, this bit defaults to 0). Reserved. Bus Configuration (only for KSZ8841-16MQL device) 1: bus width is 16 bits. 0: bus width is 8 bits. (this bit, ASYN_8bit, is only avaiable when EEPROM is enabled) ...
Page 52
... When reset, the Wake up frame 1 pattern detection is disabled. WF0E Wake up Frame 0 Enable When set, it enables the Wake up frame 0 pattern detection. When reset, the Wake up frame 0 pattern detection is disabled. Description WF0CRC0 Wake up Frame 0 CRC (lower 16 bits) The expected CRC value of a Wake up frame 0 pattern. 52 KSZ8841-16/32 MQL/MVL Rev 1.3 ...
Page 53
... Wake up frame 0. Description WF0BM3 Wake-up Frame 0 Byte Mask 3. The last 16 bytes mask covering bytes Wake-up frame 0 pattern. 53 KSZ8841-16/32 MQL/MVL bit 0 selects the 17th byte of g bit 0 selects the 33rd byte of rn. Setting bit 0 selects the 49th byte of Rev 1.3 ...
Page 54
... The first 16 bytes mask of a Wake-up frame 1 pattern. Description WF1BM1 Wake-up frame 1 Byte Mask 1. The next 16 bytes mask covering bytes Wake-up frame 1 pattern. Description WF1BM2 Wake-up frame 1 Byte Mask 2. The next 16 bytes mask covering bytes Wake-up frame 1 pattern. 54 KSZ8841-16/32 MQL/MVL Rev 1.3 ...
Page 55
... WF2BM1 Wake-up frame 2 Byte Mask 1. The next 16 bytes mask covering bytes Wake-up frame 2 pattern. 55 KSZ8841-16/32 MQL/MVL ern. Setting bit 0 selects the 49th byte Wake-up frame 1 pattern taken over the bytes specified in the frame 2 pattern. Rev 1.3 ...
Page 56
... Byte Mask 0 The first 16 byte mask of a Wake up frame 3 pattern. 56 KSZ8841-16/32 MQL/MVL ern. Setting bit 0 selects the 49th byte of taken over the bytes specified in the et standard taken over the bytes specified in the frame 3 pattern. Setting bit 0 selects the first byte of ...
Page 57
... KSZ8841M is in half-duplex mode, back-pressure flow control is enabled. When this bit is clear TXPE Transmit Padding Enable When this bit is set, the KSZ8841M automatically adds a padding field to a packet shorter than 64 bytes. 57 KSZ8841-16/32 MQL/MVL Receive Buffer capacity reaches ed, no transmit flow control is enabled. Rev 1.3 ...
Page 58
... RXEFE Receive Error Frame Enable When this bit is set, CRC error frames are allowed to be received into the RX qu When this bit is cleared, all CRC er ror frames are discarded. Reserved. 58 KSZ8841-16/32 MQL/MVL errun condition. ansmit buffer until the PAUSE frame control n eue. Rev 1.3 ...
Page 59
... Note: Software must be written to empty the RXQ memory to frame. If thi s is not done, the frame may be discarded as a result of insufficient RXQ memory. 59 KSZ8841-16/32 MQL/MVL Enable ced in a running state. ory for the next sented in units of byte. The RXQ status word. There is total 4096 bytes in RXQ. ...
Page 60
... TX Frame Pointer index to the Frame Data register for access. This field reset to next available TX frame location when the TX Frame Data has enqueued through the TXQ command register. 60 KSZ8841-16/32 MQL/MVL t transmit frame in the nt TX frame prepared in the TX buffer is queued current frame in the RXQ frame ing new RX frame ...
Page 61
... This register along with DQRL is mapped into two consecutive word locations for 16-bit buses, or one word location for 32-bit buses, to facilitate Dword move operations. 61 KSZ8841-16/32 MQL/MVL 8841M regardless of whether the pointer is even, ter register. Reading maps buses, and one uni- ...
Page 62
... Description LCIS Link Change Interrupt Status When this bit is set, it indicates that the link status has changed from link up to link down, or link down to link up. 62 KSZ8841-16/32 MQL/MVL abled. upt is disabled. g interrupt service routine or polling. The register bits Rev 1.3 ...
Page 63
... RXMF Receive Multicast Frame When set, it indicates that this frame has a multicast address (including the broadca address). RXUF Receive Unicast Frame 63 KSZ8841-16/32 MQL/MVL TXQ MAC has transmitted at least a frame on writing 1 to this bit. ived a frame from the ocess. n condition has occurred. ...
Page 64
... Early Transmit will be started on the network interface. When early transmit is enabled, se tting this field invalid, and the hardware behavior is unknown. 64 KSZ8841-16/32 MQL/MVL length is greater eeds the maximum size of 1916 bytes. use any frame ature assed to the XCR register) ...
Page 65
... Note: When the receive all (RXRA) or receive multicast (RXRM) bit is set in the RXCR, all multicast addresses are received regardless of the multicast table value. 65 KSZ8841-16/32 MQL/MVL ration is assumed. is value is defined as the six most significant bits from ast table value. ...
Page 66
... The definitions of the field values are: 00: D0 -> System is on and running 01: D1 -> Low-power state 10: D2 -> Low-power state 11: D3 (hot) -> System is off and not running 66 KSZ8841-16/32 MQL/MVL . regardless of the multicast table value. needed to return the device to ed with only PME context The o Rev 1 ...
Page 67
... This register bit sets the LEDSEL0 selection only. Port 1 LED indicators, defined as below: [LEDSEL1, LEDSEL0] [0, 0] P1LED3 ------ P1LED2 LINK/ACT P1LED1 FULL_DPX/COL P1LED0 SPEED [LEDSEL1, LEDSEL0] [1, 0] P1LED3 ACT P1LED2 LINK P1LED1 FULL_DPX/COL P1LED0 SPEED Reserved. Reserved. 67 KSZ8841-16/32 MQL/MVL [0, 1] ------ 100LINK/ACT 10LINK/ACT FULL_DPX [1, 1] ------ ------ ------ ------ Rev 1.3 ...
Page 68
... Reserved. ata for the chip function. Description Reserved. ta for the chip func tion. D escriptio n Reserved. D escriptio n I ndirect 15 ndirect da ta. gister 5 (0 x0A): IA DR5 ata for the chip function. Description Indirect Data Bit 31-16 of indirect data. 68 KSZ8841-16/32 MQL/MVL Rev 1.3 ...
Page 69
... Disable MDI disable auto M DI- normal operation. Disable Far-End-Fault 1 = disable far-end-fault detection. 69 KSZ8841-16/32 MQL/MVL Bit is same as: Bank49 0x2 bit6 Bank49 0x2 bit7 Bank49 0x2 bit11 Bank49 0x2 bit13 Bank49 0x2 bit5 Bank49 0x4 bit15 Bank49 0x2 bit9 Bank49 0x2 bit10 Bank49 0x2 bit12 Rev 1 ...
Page 70
... AN Capable 1 = auto-negotiat ion capable not auto-negotiation capable. Link Status 1 = link is up link is down. 70 KSZ8841-16/32 MQL/MVL Bit is same as: Bank49 0x2 bit14 Bank49 0x2 bit15 Bit is same as: B ank49 0x4 bit6 Bank49 0x4 bit8 Bank49 0x4 bit5 Rev 1.3 ...
Page 71
... Adv 10 Full 1 = advertise 10 full-duplex capability . not advertise 10 full-duplex capability Adv 10 Half 71 KSZ8841-16/32 MQL/MVL Bit is same as: P1ANAR nction. Bit is same as: Bank49 0x2 bit4 B ank49 0x2 bit3 Bank49 0x2 bit2 . Bank49 0x2 bit1 Bank49 0x2 bit0 Rev 1 ...
Page 72
... It is self-cleared after the VCT test is done indicates that the cable diagnostic test is completed and the status information is for read. Vct_result 72 KSZ8841-16/32 MQL/MVL Bit is same as: Bank49 0x4 bit4 Bank49 0x4 bit3 Bank49 0x4 bit2 Bank49 0x4 bit1 B ank49 0x4 bit0 1 ...
Page 73
... Remote (Near-end) Loopback (rlb perform remote loop back at PHY (RXP1/RXM1 -> TXP1/TXM1, see Figure 11 normal op eration Reserved. 73 KSZ8841-16/32 MQL/MVL same as: Bank 49 0x0 bit 15 Bank49 0x0 bit 8-0 Bit is same as: B ank49 0x04 bit13 Bank49 0x04 bit7 B ...
Page 74
... TXP1/TXM1, see F igure 11 normal operation Vc t_fault_count VCT fault count. Distance to the fault. It’s approximately 0.4m*vct_fault_count. 74 KSZ8841-16/32 MQL/MVL Is same as: Bank 47 0x00 bit 12 Bank 47 0x00 bit 14 -13 Bank 47 0x00 bit 15 Bank 47 0x02 bit 3 Bank 47 0x02 bit 2 Bank 47 0x02 bit 1 Bank 47 0x00 bit 8-0 Rev 1.3 ...
Page 75
... PHY into MDI-X mode. egotiation Enable auto negotiation is enabled. by bits 6 and 5 of the same register. eed KSZ8841-16/32 MQL/MVL Bit is same as: Bank 45 0x00 bit 0 Bank45 0x00 bit 1 Bank 45 0x00 bit 9 Bank 45 0x00 bit 2 Bank 45 0x00 bit 11 ...
Page 76
... BT half-duplex capability. half-duplex capability. half-duplex capability from rtner. on. DI-X mode. 76 KSZ8841-16/32 MQL/MVL Bit is same as: Bank 45 0x08 bit 10 Bank 45 0x08 bit 8 Bank 45 0x08 bit 7 Bank 45 0x08 bit 6 Bank 45 0x08 bit 5 Bit is same as: Bank 45 0x00 bit 5 Bank 47 0x02 bit 5 Rev 1.3 ...
Page 77
... November 2005 Bit is same as: Bank 45 0x02 bit 4 tected. Bank 47 0x02 bit 4 Bank 45 0x02 bit 5 Bank 45 0x02 bit 2 Bank 45 0x0A bit 10 low control (pause) capable. Bank 45 0x0A bit 8 Bank 45 0x0A bit 7 half-duplex capable. Bank 45 0x0A bit 6 Bank 45 0x0A bit 5 77 KSZ8841-16/32 MQL/MVL Rev 1.3 ...
Page 78
... Total Rx packets (bad packets included) that Total Rx packets (bad packets inclu Total Rx packets (bad packets included) that are between 256 and 511 octets in length Total Rx packets (bad packets included) that are between 512 and 1023 octets in length 78 KSZ8841-16/32 MQL/MVL Default 0 0 0x00000 000 ...
Page 79
... It is recommended that the software read all conds. ead clear”. That is, these c 79 KSZ8841-16/32 MQL/MVL smitted by a port uding error broadcast or valid multicast packets) including error multicast packets or valid broadcast by more than one collision counters operation) ounters will be cleared after they are read ...
Page 80
... A 0° Table 14. Operating Ratings rating. Unused inputs must always be tied to an appropriate logic voltage level (Ground 80 KSZ8841-16/32 MQL/MVL Value –0.5V to 4.0V –0. –0.5V to 4.0V — –55°C to 150°C ent damage to the device. Operation of the device this specification is not implied. ...
Page 81
... set Peak-to-peak 5MHz square wave 100Ω termination on the differential p output. 100Ω termination on the differential output.( Peak-to-peak) Table 15. Electrical Characteristics 81 KSZ8841-16/32 MQL/MVL Min Typ 3.3V 100 mA VDDIO = 3. 2.0V -10µA 2.4V + 0.95V 3ns 0ns 0.5V 0.7ns 400mV 2.4V 1.8ns Max 0 ...
Page 82
... D Y Low QMU data re gister elect reg ister) MU data reg ister) ion, it can do next Read or Write operation even the o he ADRY is low, the CPU has to keep the DN 82 KSZ8841-16/32 MQL/MVL t2 t4 valid t5 t6 valid t8 t10 Min Typ Max Unit 2 ns ...
Page 83
... November 2005 t8 valid t10 Figure 13. Asynchronous Cycle – Using ADSN e1) ion, it can do next Read or Write operation even the Y is low, the CPU has to keep the RDN/WRN low unti 83 KSZ8841-16/32 MQL/MVL valid t3 t5 valid t2 t9 t11 Min Typ Max Unit ...
Page 84
... Table 18. Asynchronous Cycle using DATACSN Timing Parameters November 2005 Figure 14. Asynchronous Cycle – Using DATACSN ow) t can do next Read or Write operation even the w, the CPU has to keep the RDN/WRN low u 84 KSZ8841-16/32 MQL/MVL t2 valid valid t8 t10 Min Typ ...
Page 85
... A1-A15, AEN, BExN[3:0] setup to ADSN t2 A1-A15, AEN, BExN[3:0] hold after ADSN rising t3 A4-A15, AEN to LDEVN delay November 2005 t1 t3 Figure 15. Address Latching Cycle for All Modes Table 19. Address Latching Timing Parameters 85 KSZ8841-16/32 MQL/MVL t2 Min Typ Max Unit Rev 1.3 ...
Page 86
... SRDYN hold to BCLK rising t10 DATACSN hold to BCLK rising t11 SWR hold to BCLK falling t12 CYCLEN hold to BCLK November 2005 Figure 16. Synchronous Burst Write Cycles – VLBUSN = 1 Table 20. Synchronous Burst Write Timing Parameters 86 KSZ8841-16/32 MQL/MVL Min Typ Max Unit ...
Page 87
... SWR hold to BCLK falling t12 CYCLEN hold to BCLK November 2005 data0 Figure 17. Synchronous Burst Read Cycles – VLBUSN = 1 Table 21. Synchronous Burst Read Timing 87 KSZ8841-16/32 MQL/MVL t10 t11 t12 data1 data2 data3 Min Typ Max Unit ...
Page 88
... SRDYN hold to BCLK t11 RDYRTNN setup to BCLK t12 RDYRTNN hold to BCLK Table November 2005 t2 valid t1 t5 Figure 18. Synchronous Write Cycle – VLBUSN = 0 22. Synchronous Write (VLBUSN = 0) Timing Paramete 88 KSZ8841-16/32 MQL/MVL valid t9 t10 t11 t12 Min Typ Max Unit ...
Page 89
... SRDYN hold to BCLK t10 RDYRTNN setup to LCLK rising t11 RDYRTNN hold after LCLK rising Table 23. Synchronous Read (VLBUSN = 0) Timing Parameters November 2005 t2 valid t1 t5 Figure 19. Synchronous Read Cycle – VLBUSN = 0 89 KSZ8841-16/32 MQL/MVL valid t8 t9 t10 t11 Min Typ Ma ...
Page 90
... Clock pulse to CTC clock pulse Number Clock/Data pulses per burst November 2005 Figure 20. Auto Negotiation Timing Min Typ 100 55.5 64 111 128 of 17 Table 24. Auto Negotiation Timing Para 90 KSZ8841-16/32 MQL/MVL Max Unit 69.5 µs 139 µ ters Rev 1.3 ...
Page 91
... KSZ8841M supply voltages (3.3V). The reset timing requirement is summarized in the Figure 21 and Table 25. Symbol sr Stable supply t November 2005 Supply Voltage tsr RST_N Figure 21. Reset Timing Parameter voltages to reset High Table 25. Reset Timing Parameters 91 KSZ8841-16/32 MQL/MVL Min Max Unit 10 ms Rev 1.3 ...
Page 92
... Start bit Timing Description Parameter tcyc Clock cycle ts Setup time th Hold time November 2005 D15 Figure 22. EEPROM Read Cycle Timin Min Typ Table 26. EEPROM Timing Parameters 92 KSZ8841-16/32 MQL/MVL tcyc ts D1 D13 D14 g Diag ram Max Unit µ Rev 1.3 ...
Page 93
... H1102 H1260 HB726 S558-5999-U7 LF8505 L F-H41S Table ualified Single Port Magnetic tal Value 25 ± Table 29. Typical Reference Crystal Characteristics 93 KSZ8841-16/32 MQL/MVL Test Condition 100mV, 100kHz, 8mA 1MHz (min) 0MHz – 65MHz Number of Port Yes 1 Yes 1 Yes 1 Yes 1 Yes 1 Yes 1 ...
Page 94
... Micrel Confidential Package Information November 2005 Figure 23. 128-Pin PQFP Package 94 KSZ8841-16/32 MQL/MVL Rev 1.3 ...
Page 95
... Micrel Confidential November 2005 Figure 24. Optional 128-Pin LQFP Package 95 KSZ8841-16/32 MQL/MVL Rev 1.3 ...
Page 96
... An Ethernet port connection that allows network hubs or switches to connect to other hubs or switches without a null-modem, or crossover, cable. MDI provides the standard interface to a particular media (copper or fiber) and is therefore 'media dependent.' 96 KSZ8841-16/32 MQL/MVL . CRC for Rev 1.3 ...
Page 97
... Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any da mages resulting from such use or sale. © 2005 M icrel, Incorporated. 97 KSZ8841-16/32 MQL/MVL ange operating parameters in network nodes (static isters as defined in the IEEE 802.3 a VLAN reference oscillator so that it maintains a en MAC/PHY interface and the system ning 4 twisted pairs of wires ...