KSZ8841-16 Micrel Semiconductor, KSZ8841-16 Datasheet - Page 84

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KSZ8841-16

Manufacturer Part Number
KSZ8841-16
Description
Single-port Ethernet Mac Controller With Non-pci Interface
Manufacturer
Micrel Semiconductor
Datasheet

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0
Asynchronous Timing using DATACSN
November 2005
Micrel Confidential
Symbol
Note1: Whe
AR
the ARDY r
t10
DY is
(Read Cycle)
( Write Cycle)
t1
t2
t3
t4
t5
t6
t7
t8
t9
RDN, WRN
Write Data
DATACSN
Read Data
low
ARDY
ARDY
eturns to high.
n CPU finished current Read or Write operation, i
Parameter
DATACSN setup to RDN, WRN active
DATACSN hold after RDN, WRN inactive (assume
ADSN tied L
Read data hold to ARDY rising
Read data to RDN hold
Write data setup to WRN inactive
Write data hold after WRN inactive
Read active to ARDY Low
Write inactive to ARDY Low
ARDY low (wait time) in read cycle (Note1)
(It is 0ns to read bank select register)
(It is 110ns to read QMU data register)
(It is 0ns to write bank select register)
(It is 85ns to write QMU data register)
ARDY low (wait time) in write cycle (Note1)
. During Read or Write operation if the ADRY is lo
Table 18. Asynchronous Cycle using DATACSN Timing Parameters
Figure 14. Asynchronous Cycle – Using DATACSN
ow)
t1
t7
84
t9
t can do next Read or Write operation even the
w, the CPU has to keep the RDN/WRN low u
t3
t5
valid
Min
2
0
4
4
2
0
0
valid
t2
t6
t8
Typ
t4
1
8
10
5
t10
Max
0.8
8
8
KSZ8841-16/32 MQL/MVL
Unit
ntil
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev 1.3

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