KSZ8841-16 Micrel Semiconductor, KSZ8841-16 Datasheet - Page 30

• Manufacturer Part Number: KSZ8841-16
• Description: Single-port Ethernet Mac Controller With Non-pci Interface
• Manufacturer: Micrel Semiconductor

2. Interfacing with the system/host relyin
3. Interfacing with the system/host relying on central decoding (KSZ8841-32MQL only).
Synch
For synchronous transfers, the synchron
asynchronous dedicated signals RDN and WRN are de-asserted and stay at the same logic level throughout the entire
synchronous transfer.
The sy
burst transfers. The VLBus-like interface s
VLBus-like or EISA-like burst transfer –
interface is for EISA-like burst transfer.
BIU Summation
Figure 9 shows the mappin
Figure 10 shows the connection for different data bus sizes.
Note: For the 8-bit data bus mode, the interna
address will enable the BE0N and an odd address will enable the BE1N.
November 2005
Micrel Confidential
in Figure 12. No additional address latch is required, therefore ADSN should be connected Low. The BIU decodes
A[15:4] and qualifies with AEN (Addre
host utilizes the rising edge of RDN to
transfer: The typical example for this application is EISA-like bus (non-burst) interface as shown in the Figure 13. This
type of interface requires ADSN to latch the address on the rising edge. The BIU decodes latched A[15:4] and
qualifies with AEN to determine if the
first case.
Th
or within the processor. Connecting t
decoder. When the DATACSN is asserted, it only allows access to the Data Register in 32 bits and BE3N, BE2N,
BE1N, and BE0N are ignored as shown in the Figure 14. No other registers can be accessed by asserting DATACSN.
The data transfer is the same as in the
wait state, the BIU will assert ARDY to
•
•
e typical
ronous
nchronous
For VLBus-like transfer interface
This interface is used in an architecture in which the device’s local decoder is utilized; that is, the BIU decodes
latch
target. No burst is supported
CYC
delay
ready
the system/host has latched the re
timing waveform is shown in Figure 18
For EISA-like burst transfer in
The SWR is connected to IORC# in EISA to indicate the burst read and CYCLEN is connected to IOWC# in EISA
to indicate the burst write. Note that in this application, both the system/host/memory and KSZ8841M are capable
of inserting wait states. For system/host/memory to insert a wait state,
KSZ8841M to insert the wait state, assert the SRDYN signal. The timing waveform is shown in Figure 16 and
Figure 17.
ed A[15:4]
LEN in this
of ADSN.
to finish the cycle, it asserts
Interface
example or this applicatio
interfa
ce
an
Th
ap
f
d qualifies with
ere is a handsh
plication is use
g from ISA-like, EISA-like and VLBus-like transactions to the chip’s BIU.
mainly support
in this application. The M/nIO signal connection in VLBus is routed to AEN. The
terface (VLBUSN = 1):
he chip select (CS) from system/host to DATACSN bypasses the
ss Enable) to determine if the KSZ8841M device is the intended ta
g on local
s two applications, one for VLB
d to sample the SWR
n is for an embedded processor having a central decode
if VLBUSN = 0, the interface is for VLBus-like transfer; if VLBUS
latch read data and the BIU will use rising edge of W
KSZ8841M device is the inte
aking process to end
SRDYN
prolong the cycle.
ous dedicated signals CYCLEN, SWR, and RDYRTNN will
upports only single-data transfer. The pin option VLBUSN determ
ad data. The KSZ8841M holds the read data
AEN (Addr
first case. Independent of the type of asynchronous interface used.
(VLBUSN = 0):
l inverter is enabled and connected between BE0N and BE1N, so an even
and Figure 19.
.
The system/h
device decoding but not having stable address throughout the entire
ess Enable) to determine if the KSZ8841M device is the intended
30
the cycle of VLBus-like transfers. When the KSZ8841M is
signal when it is asserted. Usually, CYCLEN is one clock
ost acknowledges SRDYN by asserting RDYRTNN after
nded target. The data transfer is the same as the
us-like and the other for EISA-like (DMA type C)
assert the RDYRTNN signal; for the
until RDYRTNN is asserted. The
KSZ8841-16/32 MQL/MVL
RN to latch write data.
r on the system board
toggle but the
rget. The
ines if it is a
local device
N = 1, the
To insert a
Rev 1.3