KSZ8841-16 Micrel Semiconductor, KSZ8841-16 Datasheet - Page 58

• Manufacturer Part Number: KSZ8841-16
• Description: Single-port Ethernet Mac Controller With Non-pci Interface
• Manufacturer: Micrel Semiconductor

Bank 16 Transmit Status Register (0x02): TXSR
This register keeps the status of the last transmitted frame.
Bank 16 Receive Control Register (0x04): RXCR
This register holds control information programmed by the CPU to control the receive function.
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1
0
Bit
15
14
13
12
11-6
5-0
Bit
15-11
10
9
8
0x0
0x0
Default Value
0x0
0x0
0x0
0x0
-
-
Default Value
-
0x0
0x0
-
RW
RW
R/W
RO
RO
RO
RO
RO
RO
R/W
RO
RW
RW
RO
Note: Setting this bit requires enabling the add CRC feature to avoid CRC errors for
the transmit packet.
TXCE Transmit CRC Enable
When this bit is set, the KSZ8841M automatically adds a CRC checksum field to the
end of a transmit frame.
TXE Transmit Enable
When this
When reset, the transmit process
of the current frame is completed.
Description
Reserved.
TXUR Tran
This bit is set when underrun occ
Note: This is a fatal status. Software should guarantee that no underrun conditio
occurred when enabling the early transmit function. The system or the QMU requires a
reset or restart to recover from an und
To aviod transmit underun condition, the user has to make sure that the host interface
speed (bandwidth) is faster than the ethernet port.
TXLC Transmit Late Collision
This bit is set when a transmit Late Collision occurs.
TXMC Tra
This bit is set when a transmit Ma
Reserved.
TXFID Transmit Frame ID
This field identifies the transmitted frame. All of the transmit status information in this
register belongs to the frame w
Description
Reserved.
RXFCE Receive Flow Control Enable
When this b
and the KSZ
the outgoing packets are pending in the tr
timer expires. This field has no meaning in half-duplex mode and should be
programmed to 0.
When this bit is cleared, flow control is not enabled.
RXEFE Receive Error Frame Enable
When this bit is set, CRC error frames are allowed to be received into the RX qu
When this bit is cleared, all CRC er
Reserved.
nsmit Maximum Collision
bit is set, the transmit module is enabled and placed in a running state.
smit Underrun
it is set and the KSZ8841M is in full-duplex mode, flow control is enabled,
8841M will acknowledge a PAUSE frame from the receive interface; i.e.,
58
ith this ID.
urs.
ximum Collision is reached.
is placed in the stopped state after the transmission
ror frames are discarded.
errun condition.
ansmit buffer until the PAUSE frame control
KSZ8841-16/32 MQL/MVL
n
eue.
Rev 1.3