KSZ8841-16 Micrel Semiconductor, KSZ8841-16 Datasheet - Page 59

• Manufacturer Part Number: KSZ8841-16
• Description: Single-port Ethernet Mac Controller With Non-pci Interface
• Manufacturer: Micrel Semiconductor

Bank 16 TXQ Memory Information
This register indicates the amount of free memory available in the TXQ of the QMU module.
Bank 16 RXQ Memory Information Register (0x0A): RXMIR
This register indicates the amount o
November 2005
Micrel Confidential
Bit
7
6
5
4
3
2
1
0
Bit
15-13
12-0
Bit
15-13
12-0
Default Value
0x0
0x0
0x0
0x0
0x0
0x0
-
0x0
De
-
-
Default Value
-
-
fault Value
R/W
RW
RW
RW
RW
RW
RW
RO
RW
R/W
RO
RO
R/W
RO
RO
Description
RXBE Receive Broa
When this bit is set, the RX mo
RXME Receive Multicast Enable
When this bit is set, the
broadcast frames).
RXUE Receive Unicast
When this bit is set, the RX module receives unicast frames that match the 48-bit
Station MAC address of the module.
RXRA Receive All
When this bit is set, the KS
frame’s destination address
RXSCE Receive Strip CRC
When this b
cleared, the CRC is stored in
QMU Receive Multicast Hash-Table
When this bit is set, this bit enables the RX function to receive multicast frames tha
pass the CRC Hash filtering mechanism.
Reserved.
RXE Receive Enable
When this bit is set, the RX block is enabled and pla
When this bit is cleared, the recei
completing reception of the current frame.
Description
Reserved.
TXMA Transmit Memory Available
The amount of me
used for both frame payload, control word.
Note: Software must be written to ensure that there is enough mem
transmit frame
f free memory available in the RXQ of the QMU module.
Description
Reserved.
RXMA Receive Pa
The amount of Receive packet data available is repre
memory is used for both frame payload,
This counter will update after a complete packet is received and also issues an
interrupt when receive interrupt enable IER[13] in Bank 18 is set.
Note: Software must be written to empty the RXQ memory to
frame. If thi
memory.
Register (0x08): TXMIR
s is not done, the frame may be discarded as a result of insufficient RXQ
it is set, the KSZ8841M strips the CRC on the received frames. Once
including control information before transmit data is written to the TXQ.
mory available is represented in units of byte. The TXQ memory is
cket Data Available
dcast Enable
59
RX module receives all the multicast frames (including
Z8841M receives all incoming frames, regardless of the
.
memory following the packet.
dule receives all the broadcast frames.
ve process is placed in the stopped state upon
Enable
status word. There is total 4096 bytes in RXQ.
ced in a running state.
sented in units of byte. The RXQ
allow for the new RX
KSZ8841-16/32 MQL/MVL
ory for the next
t
Rev 1.3